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Thu, 15 Jan 2026 08:47:03 -0800 (PST) X-Received: by 2002:a17:90b:1e47:b0:349:8184:af8b with SMTP id 98e67ed59e1d1-35272ec4d3amr45084a91.7.1768495622637; Thu, 15 Jan 2026 08:47:02 -0800 (PST) Received: from [192.168.0.195] ([49.204.29.18]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-352677c90easm2484312a91.4.2026.01.15.08.46.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 Jan 2026 08:47:02 -0800 (PST) Message-ID: <4bfc5d1a-d200-439b-8e0b-9afb8122eba8@oss.qualcomm.com> Date: Thu, 15 Jan 2026 22:16:56 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 09/10] arm64: dts: qcom: kaanapali: Add support for MM clock controllers for Kaanapali To: Dmitry Baryshkov , Jingyi Wang Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, 20260114-knp-remoteproc-v4-0-fcf0b04d01af@oss.qualcomm.com References: <20260114-knp-dts-misc-v3-0-a6cc9e45de93@oss.qualcomm.com> <20260114-knp-dts-misc-v3-9-a6cc9e45de93@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTE1MDEyOCBTYWx0ZWRfXxbvAmNcl86b/ u5v6ROCsdmXWxjLcMZXdt9QRrmjIVV9oLeAl+w4p2VS6LzocwSYjKnYS/cheKr6nNFiu9nrtHwJ DNQFphQccmPTsGEpv/jwvqUMWYQC8cmgMrrMbVy8xApGd0dFFlPepvT5mgE/oIVt0TtIpxwPRF8 16tg7rWbWADr4qr9HB+Gdj87TI56QJ0ef0kuiNxjTGfjGXGm7ldHlK5OKJSyNing/4kWHBtYvmr jYCYVokcfTswrAdYNAg4MWAQJ/mdPSBDePtd/ocatlJmPcIvTtonu3VvjzRDGwKop5Pj9ZeI9Sf wW9h4nUfpJuNTKT/D1b7JPQ28IFGLjlF7prM5LZi9uKv2SUOWUDG5v8Zyyp6LDMrYz2+yjROAKA IuSVwgXF/wbI9MfKMYmTr3tq/SnVdnjN7E0Fj1Epase7SCh6BReBrQC74e5HLuvaZb9XsY4pgm5 ffPo0VKvn2ddubiHdGQ== X-Proofpoint-ORIG-GUID: 7jk-mnPzDJ8OXrcYSyy-NOFY8tKSnamH X-Authority-Analysis: v=2.4 cv=W6Y1lBWk c=1 sm=1 tr=0 ts=69691a08 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=sDpHl6b8cZmcZdfeLADyyQ==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=1aPxvton2V9lDOEFgK0A:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-GUID: 7jk-mnPzDJ8OXrcYSyy-NOFY8tKSnamH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-15_05,2026-01-15_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 phishscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 malwarescore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601150128 On 1/15/2026 12:49 PM, Dmitry Baryshkov wrote: > On Wed, Jan 14, 2026 at 10:49:11PM -0800, Jingyi Wang wrote: >> From: Taniya Das >> >> Add the device nodes for the multimedia clock controllers(cambistmclkcc, > > Somebody took away a whitespace from the previous line. Will fix in the next patch. > >> camcc, dispcc, videocc, gpucc and gxclkctl). >> >> Signed-off-by: Taniya Das >> Signed-off-by: Jingyi Wang >> --- >> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 102 ++++++++++++++++++++++++++++++++ >> 1 file changed, 102 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi >> index 30705483ca20..8689715ae24f 100644 >> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi >> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi >> @@ -3,7 +3,13 @@ >> * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. >> */ >> >> +#include >> +#include >> +#include >> #include >> +#include >> +#include >> +#include >> #include >> #include >> #include >> @@ -1594,6 +1600,24 @@ aggre_noc: interconnect@16e0000 { >> <&rpmhcc RPMH_IPA_CLK>; >> }; >> >> + cambistmclkcc: clock-controller@1760000 { >> + compatible = "qcom,kaanapali-cambistmclkcc"; >> + reg = <0x0 0x1760000 0x0 0x6000>; > > 0x01760000 (and similar issue with other reg properties). Sure will fix this in the next patch. > >> + >> + clocks = <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>, >> + <&bi_tcxo_div2>, >> + <&bi_tcxo_ao_div2>, >> + <&sleep_clk>; >> + >> + power-domains = <&rpmhpd RPMHPD_MMCX>, >> + <&rpmhpd RPMHPD_MX>; >> + required-opps = <&rpmhpd_opp_low_svs>, >> + <&rpmhpd_opp_low_svs>; >> + >> + #clock-cells = <1>; >> + #reset-cells = <1>; > > Is it a reset controller? > Yes, it can support. >> + }; >> + >> mmss_noc: interconnect@1780000 { >> compatible = "qcom,kaanapali-mmss-noc"; >> reg = <0x0 0x01780000 0x0 0x5b800>; > >> + >> + dispcc: clock-controller@9ba2000 { >> + compatible = "qcom,kaanapali-dispcc"; >> + reg = <0x0 0x9ba2000 0x0 0x20000>; >> + clocks = <&bi_tcxo_div2>, >> + <&bi_tcxo_ao_div2>, >> + <&gcc GCC_DISP_AHB_CLK>, >> + <&sleep_clk>, >> + <0>, <0>, <0>, <0>, >> + <0>, <0>, <0>, <0>, >> + <0>, <0>, <0>, <0>; > > One zero per line. Or two, if you want to pair DP and DSI clock entries. > Sure, will update. >> + >> + power-domains = <&rpmhpd RPMHPD_MMCX>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + >> + #clock-cells = <1>; >> + #power-domain-cells = <1>; >> + #reset-cells = <1>; >> + }; >> + >> pdc: interrupt-controller@b220000 { >> compatible = "qcom,kaanapali-pdc", "qcom,pdc"; >> reg = <0x0 0x0b220000 0x0 0x10000>, >> >> -- >> 2.25.1 >> > -- Thanks, Taniya Das