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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa625e4db84sm120014166b.41.2024.12.05.09.19.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Dec 2024 09:19:24 -0800 (PST) Message-ID: <4c1fe789-5190-465d-bb41-3fe1534d2523@oss.qualcomm.com> Date: Thu, 5 Dec 2024 18:19:21 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v14 7/8] arm64: dts: qcom: ipq9574: Add SPI nand support To: Md Sadre Alam , broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, manivannan.sadhasivam@linaro.org, linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org Cc: quic_srichara@quicinc.com, quic_varada@quicinc.com References: <20241120091507.1404368-1-quic_mdalam@quicinc.com> <20241120091507.1404368-8-quic_mdalam@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20241120091507.1404368-8-quic_mdalam@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: VoLx1v5bsq4rwI_ec4o0QK7UuI6vOeUO X-Proofpoint-ORIG-GUID: VoLx1v5bsq4rwI_ec4o0QK7UuI6vOeUO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=999 spamscore=0 adultscore=0 suspectscore=0 malwarescore=0 mlxscore=0 impostorscore=0 bulkscore=0 phishscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412050126 On 20.11.2024 10:15 AM, Md Sadre Alam wrote: > Add SPI NAND support for ipq9574 SoC. > > Signed-off-by: Md Sadre Alam > --- [...] Feel free to put dt patches in a separate series after Miquel picks up the mtd changes > &usb_0_dwc3 { > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > index d1fd35ebc4a2..45fb26bc9480 100644 board and dtsi patches should be 2 separate ones > --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > @@ -330,6 +330,33 @@ tcsr: syscon@1937000 { > reg = <0x01937000 0x21000>; > }; > > + qpic_bam: dma-controller@7984000 { > + compatible = "qcom,bam-v1.7.0"; > + reg = <0x7984000 0x1c000>; Please pad the address part to 8 hex digits with leading zeroes > + interrupts = ; > + clocks = <&gcc GCC_QPIC_AHB_CLK>; > + clock-names = "bam_clk"; > + #dma-cells = <1>; > + qcom,ee = <0>; > + status = "disabled"; > + }; > + > + qpic_nand: spi@79b0000 { > + compatible = "qcom,ipq9574-snand"; > + reg = <0x79b0000 0x10000>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&gcc GCC_QPIC_CLK>, > + <&gcc GCC_QPIC_AHB_CLK>, > + <&gcc GCC_QPIC_IO_MACRO_CLK>; > + clock-names = "core", "aon", "iom"; > + dmas = <&qpic_bam 0>, > + <&qpic_bam 1>, > + <&qpic_bam 2>; > + dma-names = "tx", "rx", "cmd"; Please make clock/dma names a vertical list, like clocks/dmas Also, is it okay not to use any of the GCC_QPIC_BCR/ GCC_QPIC_AHB_ARES/GCC_QPIC_ARES resets found in GCC? Konrad