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Bottomley" , "Martin K. Petersen" , Sai Krishna Potthuri , "moderated list:ARM/ZYNQ ARCHITECTURE" , "open list:SCSI SUBSYSTEM" References: Content-Language: en-US From: Michal Simek Autocrypt: addr=michal.simek@amd.com; keydata= xsFNBFFuvDEBEAC9Amu3nk79+J+4xBOuM5XmDmljuukOc6mKB5bBYOa4SrWJZTjeGRf52VMc howHe8Y9nSbG92obZMqsdt+d/hmRu3fgwRYiiU97YJjUkCN5paHXyBb+3IdrLNGt8I7C9RMy svSoH4WcApYNqvB3rcMtJIna+HUhx8xOk+XCfyKJDnrSuKgx0Svj446qgM5fe7RyFOlGX/wF Ae63Hs0RkFo3I/+hLLJP6kwPnOEo3lkvzm3FMMy0D9VxT9e6Y3afe1UTQuhkg8PbABxhowzj SEnl0ICoqpBqqROV/w1fOlPrm4WSNlZJunYV4gTEustZf8j9FWncn3QzRhnQOSuzTPFbsbH5 WVxwDvgHLRTmBuMw1sqvCc7CofjsD1XM9bP3HOBwCxKaTyOxbPJh3D4AdD1u+cF/lj9Fj255 Es9aATHPvoDQmOzyyRNTQzupN8UtZ+/tB4mhgxWzorpbdItaSXWgdDPDtssJIC+d5+hskys8 B3jbv86lyM+4jh2URpnL1gqOPwnaf1zm/7sqoN3r64cml94q68jfY4lNTwjA/SnaS1DE9XXa XQlkhHgjSLyRjjsMsz+2A4otRLrBbumEUtSMlPfhTi8xUsj9ZfPIUz3fji8vmxZG/Da6jx/c a0UQdFFCL4Ay/EMSoGbQouzhC69OQLWNH3rMQbBvrRbiMJbEZwARAQABzSlNaWNoYWwgU2lt ZWsgKEFNRCkgPG1pY2hhbC5zaW1la0BhbWQuY29tPsLBlAQTAQgAPgIbAwULCQgHAgYVCgkI CwIEFgIDAQIeAQIXgBYhBGc1DJv1zO6bU2Q1ajd8fyH+PR+RBQJn8lwDBQkaRgbLAAoJEDd8 fyH+PR+RCNAP/iHkKbpP0XXfgfWqf8yyrFHjGPJSknERzxw0glxPztfC3UqeusQ0CPnbI85n uQdm5/zRgWr7wi8H2UMqFlfMW8/NH5Da7GOPc26NMTPA2ZG5S2SG2SGZj1Smq8mL4iueePiN x1qfWhVm7TfkDHUEmMAYq70sjFcvygyqHUCumpw36CMQSMyrxyEkbYm1NKORlnySAFHy2pOx nmXKSaL1yfof3JJLwNwtaBj76GKQILnlYx9QNnt6adCtrZLIhB3HGh4IRJyuiiM0aZi1G8ei 2ILx2n2LxUw7X6aAD0sYHtNKUCQMCBGQHzJLDYjEyy0kfYoLXV2P6K+7WYnRP+uV8g77Gl9a IuGvxgEUITjMakX3e8RjyZ5jmc5ZAsegfJ669oZJOzQouw/W9Qneb820rhA2CKK8BnmlkHP+ WB5yDks3gSHE/GlOWqRkVZ05sUjVmq/tZ1JEdOapWQovRQsueDjxXcMjgNo5e8ttCyMo44u1 pKXRJpR5l7/hBYWeMlcKvLwByep+FOGtKsv0xadMKr1M6wPZXkV83jMKxxRE9HlqWJLLUE1Q 0pDvn1EvlpDj9eED73iMBsrHu9cIk8aweTEbQ4bcKRGfGkXrCwle6xRiKSjXCdzWpOglNhjq 1g8Ak+G+ZR6r7QarL01BkdE2/WUOLHdGHB1hJxARbP2E3l46zsFNBFFuvDEBEACXqiX5h4IA 03fJOwh+82aQWeHVAEDpjDzK5hSSJZDE55KP8br1FZrgrjvQ9Ma7thSu1mbr+ydeIqoO1/iM fZA+DDPpvo6kscjep11bNhVa0JpHhwnMfHNTSHDMq9OXL9ZZpku/+OXtapISzIH336p4ZUUB 5asad8Ux70g4gmI92eLWBzFFdlyR4g1Vis511Nn481lsDO9LZhKyWelbif7FKKv4p3FRPSbB vEgh71V3NDCPlJJoiHiYaS8IN3uasV/S1+cxVbwz2WcUEZCpeHcY2qsQAEqp4GM7PF2G6gtz IOBUMk7fjku1mzlx4zP7uj87LGJTOAxQUJ1HHlx3Li+xu2oF9Vv101/fsCmptAAUMo7KiJgP Lu8TsP1migoOoSbGUMR0jQpUcKF2L2jaNVS6updvNjbRmFojK2y6A/Bc6WAKhtdv8/e0/Zby iVA7/EN5phZ1GugMJxOLHJ1eqw7DQ5CHcSQ5bOx0Yjmhg4PT6pbW3mB1w+ClAnxhAbyMsfBn XxvvcjWIPnBVlB2Z0YH/gizMDdM0Sa/HIz+q7JR7XkGL4MYeAM15m6O7hkCJcoFV7LMzkNKk OiCZ3E0JYDsMXvmh3S4EVWAG+buA+9beElCmXDcXPI4PinMPqpwmLNcEhPVMQfvAYRqQp2fg 1vTEyK58Ms+0a9L1k5MvvbFg9QARAQABwsF8BBgBCAAmAhsMFiEEZzUMm/XM7ptTZDVqN3x/ If49H5EFAmfyXCkFCRpGBvgACgkQN3x/If49H5GY5xAAoKWHRO/OlI7eMA8VaUgFInmphBAj fAgQbW6Zxl9ULaCcNSoJc2D0zYWXftDOJeXyVk5Gb8cMbLA1tIMSM/BgSAnT7As2KfcZDTXQ DJSZYWgYKc/YywLgUlpv4slFv5tjmoUvHK9w2DuFLW254pnUuhrdyTEaknEM+qOmPscWOs0R dR6mMTN0vBjnLUeYdy0xbaoefjT+tWBybXkVwLDd3d/+mOa9ZiAB7ynuVWu2ow/uGJx0hnRI LGfLsiPu47YQrQXu79r7RtVeAYwRh3ul7wx5LABWI6n31oEHxDH+1czVjKsiozRstEaUxuDZ jWRHq+AEIq79BTTopj2dnW+sZAsnVpQmc+nod6xR907pzt/HZL0WoWwRVkbg7hqtzKOBoju3 hftqVr0nx77oBZD6mSJsxM/QuJoaXaTX/a/QiB4Nwrja2jlM0lMUA/bGeM1tQwS7rJLaT3cT RBGSlJgyWtR8IQvX3rqHd6QrFi1poQ1/wpLummWO0adWes2U6I3GtD9vxO/cazWrWBDoQ8Da otYa9+7v0j0WOBTJaj16LFxdSRq/jZ1y/EIHs3Ysd85mUWXOB8xZ6h+WEMzqAvOt02oWJVbr ZLqxG/3ScDXZEUJ6EDJVoLAK50zMk87ece2+4GWGOKfFsiDfh7fnEMXQcykxuowBYUD0tMd2 mpwx1d8= In-Reply-To: Content-Type: text/plain; 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Each iteration is a full firmware round-trip > (PM_IOCTL/IOCTL_READ_REG of a protected PMC_IOU_SLCR register), so the > loop can issue up to a million EEMI calls, and it hard-codes the wait > policy inside the controller driver. > > Introduce coarse blocking helpers, zynqmp_pm_wait_mphy_tx_rx_config_ready() > and zynqmp_pm_wait_sram_init_done(), that take a caller-supplied timeout > budget and contain the poll loop. The loop is EEMI-specific (legacy > firmware only exposes the per-read status primitive) so it lives in the > firmware driver, keeping the UFS driver backend-agnostic: a future > backend can offload the wait to the platform in a single call without > touching the controller driver again. The existing per-read primitives stay > exported, so the current EEMI interface is unchanged. > > The timeout budget remains owned by the UFS driver (the consumer that > knows the hardware) and is passed down, so EEMI and any future backend > stay consistent. > > Signed-off-by: Michal Simek > --- > > drivers/firmware/xilinx/zynqmp-ufs.c | 70 ++++++++++++++++++++++-- > drivers/ufs/host/ufs-amd-versal2.c | 46 ++++------------ > include/linux/firmware/xlnx-zynqmp-ufs.h | 8 +-- > 3 files changed, 82 insertions(+), 42 deletions(-) > > diff --git a/drivers/firmware/xilinx/zynqmp-ufs.c b/drivers/firmware/xilinx/zynqmp-ufs.c > index 85da8a822f3a..81ccf61a037c 100644 > --- a/drivers/firmware/xilinx/zynqmp-ufs.c > +++ b/drivers/firmware/xilinx/zynqmp-ufs.c > @@ -5,6 +5,7 @@ > * Copyright (C) 2025 Advanced Micro Devices, Inc. > */ > > +#include > #include > #include > > @@ -33,7 +34,7 @@ > * > * Return: Returns 0 on success or error value on failure. > */ > -int zynqmp_pm_is_mphy_tx_rx_config_ready(bool *is_ready) > +static int zynqmp_pm_is_mphy_tx_rx_config_ready(bool *is_ready) > { > u32 regval; > int ret; > @@ -53,7 +54,6 @@ int zynqmp_pm_is_mphy_tx_rx_config_ready(bool *is_ready) > > return ret; > } > -EXPORT_SYMBOL_GPL(zynqmp_pm_is_mphy_tx_rx_config_ready); > > /** > * zynqmp_pm_is_sram_init_done - check SRAM initialization > @@ -61,7 +61,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_is_mphy_tx_rx_config_ready); > * > * Return: Returns 0 on success or error value on failure. > */ > -int zynqmp_pm_is_sram_init_done(bool *is_done) > +static int zynqmp_pm_is_sram_init_done(bool *is_done) > { > u32 regval; > int ret; > @@ -81,7 +81,69 @@ int zynqmp_pm_is_sram_init_done(bool *is_done) > > return ret; > } > -EXPORT_SYMBOL_GPL(zynqmp_pm_is_sram_init_done); > + > +/** > + * zynqmp_pm_wait_mphy_tx_rx_config_ready - wait for M-PHY TX-RX config ready > + * @timeout_us: Caller-supplied timeout budget in microseconds > + * > + * Poll the M-PHY TX-RX configuration-ready status until it settles or the > + * timeout elapses. The poll loop is EEMI-specific (legacy firmware only offers > + * the per-read status primitive), so it lives here in the firmware driver > + * rather than in the UFS controller driver; an SCMI-based backend can instead > + * offload the wait to the platform in a single call. The timeout budget is > + * owned by the caller (UFS driver), keeping the policy with the consumer. > + * > + * Return: Returns 0 once ready, -ETIMEDOUT on timeout, or error value. > + */ > +int zynqmp_pm_wait_mphy_tx_rx_config_ready(u32 timeout_us) > +{ > + bool is_ready; > + int ret; > + > + while (timeout_us--) { > + ret = zynqmp_pm_is_mphy_tx_rx_config_ready(&is_ready); > + if (ret) > + return ret; > + > + if (!is_ready) > + return 0; > + > + usleep_range(1, 5); > + } > + > + return -ETIMEDOUT; > +} > +EXPORT_SYMBOL_GPL(zynqmp_pm_wait_mphy_tx_rx_config_ready); > + > +/** > + * zynqmp_pm_wait_sram_init_done - wait for SRAM initialization to complete > + * @timeout_us: Caller-supplied timeout budget in microseconds > + * > + * Poll the SRAM initialization-done status until it is set or the timeout > + * elapses. As with the M-PHY wait, the poll loop is EEMI-specific and kept in > + * the firmware driver so the UFS controller driver stays backend-agnostic. > + * > + * Return: Returns 0 once done, -ETIMEDOUT on timeout, or error value. > + */ > +int zynqmp_pm_wait_sram_init_done(u32 timeout_us) > +{ > + bool is_done; > + int ret; > + > + while (timeout_us--) { > + ret = zynqmp_pm_is_sram_init_done(&is_done); > + if (ret) > + return ret; > + > + if (is_done) > + return 0; > + > + usleep_range(1, 5); > + } > + > + return -ETIMEDOUT; > +} > +EXPORT_SYMBOL_GPL(zynqmp_pm_wait_sram_init_done); > > /** > * zynqmp_pm_set_sram_bypass - Set SRAM bypass Control > diff --git a/drivers/ufs/host/ufs-amd-versal2.c b/drivers/ufs/host/ufs-amd-versal2.c > index 2154d6286817..dff0c2c95486 100644 > --- a/drivers/ufs/host/ufs-amd-versal2.c > +++ b/drivers/ufs/host/ufs-amd-versal2.c > @@ -225,8 +225,6 @@ static int ufs_versal2_setup_phy(struct ufs_hba *hba) > static int ufs_versal2_phy_init(struct ufs_hba *hba) > { > struct ufs_versal2_host *host = ufshcd_get_variant(hba); > - u32 time_left; > - bool is_ready; > int ret; > static const struct ufshcd_dme_attr_val rmmi_attrs[] = { > { UIC_ARG_MIB(CBREFCLKCTRL2), CBREFREFCLK_GATE_OVR_EN, DME_LOCAL }, > @@ -235,23 +233,15 @@ static int ufs_versal2_phy_init(struct ufs_hba *hba) > { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } > }; > > - /* Wait for Tx/Rx config_rdy */ > - time_left = TIMEOUT_MICROSEC; > - do { > - time_left--; > - ret = zynqmp_pm_is_mphy_tx_rx_config_ready(&is_ready); > - if (ret) > - return ret; > - > - if (!is_ready) > - break; > - > - usleep_range(1, 5); > - } while (time_left); > - > - if (!time_left) { > + /* > + * Wait for Tx/Rx config_rdy. The poll loop lives in the firmware > + * backend (EEMI today, SCMI in future) so this driver stays > + * backend-agnostic; the timeout budget stays here with the consumer. > + */ > + ret = zynqmp_pm_wait_mphy_tx_rx_config_ready(TIMEOUT_MICROSEC); > + if (ret) { > dev_err(hba->dev, "Tx/Rx configuration signal busy.\n"); > - return -ETIMEDOUT; > + return ret; > } > > ret = ufshcd_dwc_dme_set_attrs(hba, rmmi_attrs, ARRAY_SIZE(rmmi_attrs)); > @@ -264,23 +254,11 @@ static int ufs_versal2_phy_init(struct ufs_hba *hba) > return ret; > } > > - /* Wait for SRAM init done */ > - time_left = TIMEOUT_MICROSEC; > - do { > - time_left--; > - ret = zynqmp_pm_is_sram_init_done(&is_ready); > - if (ret) > - return ret; > - > - if (is_ready) > - break; > - > - usleep_range(1, 5); > - } while (time_left); > - > - if (!time_left) { > + /* Wait for SRAM init done (poll handled by the firmware backend). */ > + ret = zynqmp_pm_wait_sram_init_done(TIMEOUT_MICROSEC); > + if (ret) { > dev_err(hba->dev, "SRAM initialization failed.\n"); > - return -ETIMEDOUT; > + return ret; > } > > ret = ufs_versal2_setup_phy(hba); > diff --git a/include/linux/firmware/xlnx-zynqmp-ufs.h b/include/linux/firmware/xlnx-zynqmp-ufs.h > index d3538dd5822a..00383dd835f2 100644 > --- a/include/linux/firmware/xlnx-zynqmp-ufs.h > +++ b/include/linux/firmware/xlnx-zynqmp-ufs.h > @@ -9,17 +9,17 @@ > #define __FIRMWARE_XLNX_ZYNQMP_UFS_H__ > > #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE) > -int zynqmp_pm_is_mphy_tx_rx_config_ready(bool *is_ready); > -int zynqmp_pm_is_sram_init_done(bool *is_done); > +int zynqmp_pm_wait_mphy_tx_rx_config_ready(u32 timeout_us); > +int zynqmp_pm_wait_sram_init_done(u32 timeout_us); > int zynqmp_pm_set_sram_bypass(void); > int zynqmp_pm_get_ufs_calibration_values(u32 *val); > #else > -static inline int zynqmp_pm_is_mphy_tx_rx_config_ready(bool *is_ready) > +static inline int zynqmp_pm_wait_mphy_tx_rx_config_ready(u32 timeout_us) > { > return -ENODEV; > } > > -static inline int zynqmp_pm_is_sram_init_done(bool *is_done) > +static inline int zynqmp_pm_wait_sram_init_done(u32 timeout_us) > { > return -ENODEV; > } > --- > base-commit: 848acc8ffe1b7cd5f1bf427b93069becfebc2c9d > branch: xnext/ufs > Applied. M