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[83.9.29.77]) by smtp.gmail.com with ESMTPSA id g8-20020a19ac08000000b004f1400630d3sm1037217lfc.35.2023.06.01.02.58.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 01 Jun 2023 02:58:37 -0700 (PDT) Message-ID: <4c565a7b-3041-e3f3-7174-282348b74575@linaro.org> Date: Thu, 1 Jun 2023 11:58:35 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Subject: Re: [PATCH 2/2] arm64: dts: qcom: sm8550: add display port nodes Content-Language: en-US To: Neil Armstrong , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Andy Gross , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230601-topic-sm8550-upstream-dp-v1-0-29efe2689553@linaro.org> <20230601-topic-sm8550-upstream-dp-v1-2-29efe2689553@linaro.org> From: Konrad Dybcio In-Reply-To: <20230601-topic-sm8550-upstream-dp-v1-2-29efe2689553@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 1.06.2023 11:52, Neil Armstrong wrote: > Add the Display Port controller subnode to the MDSS node. > > Signed-off-by: Neil Armstrong > --- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 89 +++++++++++++++++++++++++++++++++++- > 1 file changed, 87 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > index 75cd374943eb..73524afc2e3a 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -2495,6 +2495,13 @@ dpu_intf2_out: endpoint { > remote-endpoint = <&mdss_dsi1_in>; > }; > }; > + > + port@2 { > + reg = <2>; > + dpu_intf0_out: endpoint { > + remote-endpoint = <&mdss_dp0_in>; > + }; > + }; > }; > > mdp_opp_table: opp-table { > @@ -2522,6 +2529,84 @@ opp-514000000 { > }; > }; > > + mdss_dp0: displayport-controller@ae90000 { > + compatible = "qcom,sm8550-dp", "qcom,sm8350-dp"; > + reg = <0 0xae90000 0 0x200>, > + <0 0xae90200 0 0x200>, > + <0 0xae90400 0 0xc00>, > + <0 0xae91000 0 0x400>, > + <0 0xae91400 0 0x400>; > + interrupt-parent = <&mdss>; > + interrupts = <12>; > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; > + clock-names = "core_iface", > + "core_aux", > + "ctrl_link", > + "ctrl_link_iface", > + "stream_pixel"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; > + assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, > + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; > + > + phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; > + phy-names = "dp"; > + > + #sound-dai-cells = <0>; > + > + operating-points-v2 = <&dp_opp_table>; > + power-domains = <&rpmhpd SM8550_CX>; MMCX > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + mdss_dp0_in: endpoint { > + remote-endpoint = <&dpu_intf0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + mdss_dp0_out: endpoint { > + }; > + }; > + }; > + > + dp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-162000000 { > + opp-hz = /bits/ 64 <162000000>; > + required-opps = <&rpmhpd_opp_low_svs>; _d1 > + }; > + > + opp-270000000 { > + opp-hz = /bits/ 64 <270000000>; > + required-opps = <&rpmhpd_opp_svs>; low_svs With these fixed: Reviewed-by: Konrad Dybcio Konrad > + }; > + > + opp-540000000 { > + opp-hz = /bits/ 64 <540000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-810000000 { > + opp-hz = /bits/ 64 <810000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > + > mdss_dsi0: dsi@ae94000 { > compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; > reg = <0 0x0ae94000 0 0x400>; > @@ -2705,8 +2790,8 @@ dispcc: clock-controller@af00000 { > <&mdss_dsi0_phy 1>, > <&mdss_dsi1_phy 0>, > <&mdss_dsi1_phy 1>, > - <0>, /* dp0 */ > - <0>, > + <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, > + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, > <0>, /* dp1 */ > <0>, > <0>, /* dp2 */ >