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[83.9.31.248]) by smtp.gmail.com with ESMTPSA id n1-20020a2e8781000000b002a7e9e4e9dcsm4631177lji.114.2023.05.01.05.44.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 May 2023 05:44:19 -0700 (PDT) Message-ID: <4c5e485a-e6ed-f5ec-f1af-3aad2efbb30a@linaro.org> Date: Mon, 1 May 2023 14:44:18 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.1 Subject: Re: [PATCH] spi: spi-geni-qcom: Correct CS_TOGGLE bit in SPI_TRANS_CFG Content-Language: en-US From: Konrad Dybcio To: Vijaya Krishna Nivarthi , agross@kernel.org, andersson@kernel.org, broonie@kernel.org, linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: quic_msavaliy@quicinc.com, dianders@chromium.org, mka@chromium.org, swboyd@chromium.org, quic_vtanuku@quicinc.com References: <1682412128-1913-1-git-send-email-quic_vnivarth@quicinc.com> <9f28dbff-ca3a-8523-5bfc-37b38bc846c3@linaro.org> <1b1b095e-8fcb-37d5-7542-48a6b55f35a1@quicinc.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 1.05.2023 14:43, Konrad Dybcio wrote: > > > On 1.05.2023 10:05, Vijaya Krishna Nivarthi wrote: >> On 4/25/2023 7:15 PM, Konrad Dybcio wrote: >>> >>> On 4/25/23 09:42, Vijaya Krishna Nivarthi wrote: >>>> The CS_TOGGLE bit when set is supposed to instruct FW to >>>> toggle CS line between words. The driver with intent of >>>> disabling this behaviour has been unsetting BIT(0). This has >>>> not caused any trouble so far because the original BIT(1) >>>> is untouched and BIT(0) likely wasn't being used. >>>> >>>> Correct this to prevent a potential future bug. >>>> >>>> Signed-off-by: Vijaya Krishna Nivarthi >>>> --- >>> >>> Has this always been the case, or did the switch to BIT(1) >>> only occur on some recent platforms? >> >> >> Thank you very much for the review.. >> >> This has always been the case. >> >> With intent of disabling CS_TOGGLE, currently, the driver is unsetting BIT(0), though it should have been BIT(1). >> >> Yet no problem was encountered because >> >> a) BIT(0) seems to be an unused bit >> >> b) BIT(1) is probably already unset because its untouched >> >> Further more, as Doug pointed we are mostly using GPIO for CS. >> >> >> Testing with the change has not caused any regressions. > Okay, with no deeper knowledge of the topic best I can give you is: > > Acked-by: Konrad Dybcio > > Also, missing: Fixes: 561de45f72bd ("spi: spi-geni-qcom: Add SPI driver support for GENI based QUP") Konrad > Konrad >> >> >> Thank you, >> >> Vijay/ >> >> >> >>> >>> Konrad >>> >>>>   drivers/spi/spi-geni-qcom.c | 2 +- >>>>   1 file changed, 1 insertion(+), 1 deletion(-) >>>> >>>> diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c >>>> index ba7be50..8a7d1c2 100644 >>>> --- a/drivers/spi/spi-geni-qcom.c >>>> +++ b/drivers/spi/spi-geni-qcom.c >>>> @@ -35,7 +35,7 @@ >>>>   #define CS_DEMUX_OUTPUT_SEL    GENMASK(3, 0) >>>>     #define SE_SPI_TRANS_CFG    0x25c >>>> -#define CS_TOGGLE        BIT(0) >>>> +#define CS_TOGGLE        BIT(1) >>>>     #define SE_SPI_WORD_LEN        0x268 >>>>   #define WORD_LEN_MSK        GENMASK(9, 0)