From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Junhao He <hejunhao3@huawei.com>,
mathieu.poirier@linaro.org, mike.leach@linaro.org,
leo.yan@linaro.org
Cc: coresight@lists.linaro.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com,
shenyang39@huawei.com, prime.zeng@hisilicon.com
Subject: Re: [PATCH] coresight: etm4x: Fix accesses to TRCSEQRSTEVR and TRCSEQSTR
Date: Tue, 10 Jan 2023 16:15:33 +0000 [thread overview]
Message-ID: <4c799bd3-ab24-c0e6-57a4-aa9acc6c46b4@arm.com> (raw)
In-Reply-To: <20230110125101.10533-1-hejunhao3@huawei.com>
On 10/01/2023 12:51, Junhao He wrote:
> The TRCSEQRSTEVR and TRCSEQSTR register is not implemented if the
> TRCIDR5.NUMSEQSTATE == 0. Skip accessing the register in such cases.
>
> Signed-off-by: Junhao He <hejunhao3@huawei.com>
This must have :
Fixes: 2e1cdfe184b5 ("coresight-etm4x: Adding CoreSight ETM4x driver")
The patch as such looks correct to me.
I will queue this.
Thanks
Suzuki
> ---
> .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++++------
> 1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 80fefaba58ee..c7a65d1524fc 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -424,8 +424,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
> for (i = 0; i < drvdata->nrseqstate - 1; i++)
> etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
> - etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
> - etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
> + if (drvdata->nrseqstate) {
> + etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
> + etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
> + }
> etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
> for (i = 0; i < drvdata->nr_cntr; i++) {
> etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
> @@ -1631,8 +1633,10 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
> for (i = 0; i < drvdata->nrseqstate - 1; i++)
> state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
>
> - state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
> - state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
> + if (drvdata->nrseqstate) {
> + state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
> + state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
> + }
> state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
>
> for (i = 0; i < drvdata->nr_cntr; i++) {
> @@ -1760,8 +1764,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
> for (i = 0; i < drvdata->nrseqstate - 1; i++)
> etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
>
> - etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
> - etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
> + if (drvdata->nrseqstate) {
> + etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
> + etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
> + }
> etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
>
> for (i = 0; i < drvdata->nr_cntr; i++) {
next prev parent reply other threads:[~2023-01-10 16:15 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-10 12:51 Junhao He
2023-01-10 14:49 ` Mike Leach
2023-01-10 16:15 ` Suzuki K Poulose [this message]
2023-01-14 8:50 ` hejunhao
2023-01-12 3:48 ` Anshuman Khandual
2023-01-14 8:49 ` hejunhao
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