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Peter Anvin" CC: References: <1bd3aab725a4e2948530095eb48b11bcc4028f8e.1693557919.git.maciej.wieczor-retman@intel.com> From: Reinette Chatre In-Reply-To: <1bd3aab725a4e2948530095eb48b11bcc4028f8e.1693557919.git.maciej.wieczor-retman@intel.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: MW4PR03CA0015.namprd03.prod.outlook.com (2603:10b6:303:8f::20) To SJ2PR11MB7573.namprd11.prod.outlook.com (2603:10b6:a03:4d2::10) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ2PR11MB7573:EE_|BN9PR11MB5386:EE_ X-MS-Office365-Filtering-Correlation-Id: 929f0e7a-a710-4c05-8bd8-08dbb3026ca2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ax8q60aDLWMvTtje4uNCMKzHv3VoTjXOG9brKlbR5Q3hhuiAv0V2/S1CVyKOHm9oyhRfCT/H869M8unI8nwhbcDJeAt1QYgQz/EHp3XNnYQxVVkhlvGUqq3cJrVi9Kc/lT7wDt1uZleY4dbrfMLI7ZlPY4Dw/e2V9ZoSj5aUWuy9VpUZF5RmfmAI3dcp9AMjImY0NcvfBm2c3blW4d07jFJfn3+kv2V/SP7j4BdqxcmNnUBDD/DWd3/WqwriBF4q9Wsv9w7ScqoGJ786uRyDFneBz7ZPAmaZ+KEUy61VAcBLHCLaCeJmHdRDKRDO2kUcQOv2sRj7H3gwve5bngqZhPcoU8ln4DwPtEPCuwpJQ/Ysueh5Y9O39k6XiKI5aLJD4kc4+Hr+y1v5ARGyYhDVdPE99V8iiZyK4lsIRg17Pa6mE4SENdg8wx2hWKpahsOp8T0F7GpFxLRV6ohF4jRAQ5RVeRXtAuHAXIWVJzVqpKkvd4gRd/CDxUblANtoPYALj+To80oqDBQqWeBuvQfyA4jzL1fVbwl50P3SObdRaCbZa2HizCoNrAmGVzsS1+zkZkEHHzXcHA5c1abXrV+E9+eJwU6xLO7sAMGKm9SeYuHIMoxsAodnu6/KuBTevXmwrYtalVYVuHDVIUlwBTubkQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SJ2PR11MB7573.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(396003)(136003)(376002)(39860400002)(366004)(346002)(1800799009)(186009)(451199024)(36756003)(31686004)(2906002)(44832011)(31696002)(86362001)(82960400001)(38100700002)(8676002)(8936002)(4326008)(83380400001)(5660300002)(26005)(41300700001)(6512007)(6486002)(6666004)(2616005)(53546011)(6506007)(478600001)(66476007)(66946007)(66556008)(110136005)(316002)(45980500001)(43740500002);DIR:OUT;SFP:1102; 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On these systems, writing non-contiguous > 1s into the schemata file will fail before resctrl passes > the value to the hardware. > > In Intel CAT CPUID.0x10.1:ECX[3] and CPUID.0x10.2:ECX[3] stopped > being reserved and now carry information about non-contiguous 1s > value support for L3 and L2 cache respectively. The CAT > capacity bitmask (CBM) supports a non-contiguous 1s value if > the bit is set. > > Replace the hardcoded non-contiguous support value with > the support learned from the hardware. Add hardcoded non-contiguous > support value to Haswell probe since it can't make use of CPUID for > Cache allocation. > > Originally-by: Fenghua Yu > Signed-off-by: Wieczor-Retman, Maciej > --- > arch/x86/kernel/cpu/resctrl/core.c | 9 ++++++--- > arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 11 +++++++---- > arch/x86/kernel/cpu/resctrl/internal.h | 9 +++++++++ > 3 files changed, 22 insertions(+), 7 deletions(-) > > diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c > index 030d3b409768..c783a873147c 100644 > --- a/arch/x86/kernel/cpu/resctrl/core.c > +++ b/arch/x86/kernel/cpu/resctrl/core.c > @@ -152,6 +152,7 @@ static inline void cache_alloc_hsw_probe(void) > r->cache.cbm_len = 20; > r->cache.shareable_bits = 0xc0000; > r->cache.min_cbm_bits = 2; > + r->cache.arch_has_sparse_bitmaps = false; > r->alloc_capable = true; > > rdt_alloc_capable = true; > @@ -267,15 +268,18 @@ static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r) > { > struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); > union cpuid_0x10_1_eax eax; > + union cpuid_0x10_x_ecx ecx; > union cpuid_0x10_x_edx edx; > - u32 ebx, ecx; > + u32 ebx; > > - cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx, &edx.full); > + cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx.full, &edx.full); > hw_res->num_closid = edx.split.cos_max + 1; > r->cache.cbm_len = eax.split.cbm_len + 1; > r->default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1; > r->cache.shareable_bits = ebx & r->default_ctrl; > r->data_width = (r->cache.cbm_len + 3) / 4; > + if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) > + r->cache.arch_has_sparse_bitmaps = ecx.split.noncont; > r->alloc_capable = true; > } > > @@ -872,7 +876,6 @@ static __init void rdt_init_res_defs_intel(void) > > if (r->rid == RDT_RESOURCE_L3 || > r->rid == RDT_RESOURCE_L2) { > - r->cache.arch_has_sparse_bitmaps = false; > r->cache.arch_has_per_cpu_cfg = false; > r->cache.min_cbm_bits = 1; > } else if (r->rid == RDT_RESOURCE_MBA) { > diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c > index b44c487727d4..782e2700290b 100644 > --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c > +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c > @@ -87,10 +87,13 @@ int parse_bw(struct rdt_parse_data *data, struct resctrl_schema *s, > > /* > * Check whether a cache bit mask is valid. > - * For Intel the SDM says: > - * Please note that all (and only) contiguous '1' combinations > - * are allowed (e.g. FFFFH, 0FF0H, 003CH, etc.). > - * Additionally Haswell requires at least two bits set. > + * On Intel CPUs, non-contiguous 1s value support is indicated by CPUID: > + * - CPUID.0x10.1:ECX[3]: L3 non-contiguous 1s value supported if 1 > + * - CPUID.0x10.2:ECX[3]: L2 non-contiguous 1s value supported if 1 > + * > + * Additionally Haswell requires at least two bits set. Since it does not > + * have CPUID enumeration support for Cache allocation the non-contiguous 1s > + * value support is disabled. The second sentence can be misinterpreted. non-contiguous 1s value support is disabled on Haswell because Haswell does not support non-contiguous 1s value, not because it does not have CPUID enumeration for RDT. > * AMD allows non-contiguous bitmasks. (connecting to comments in following patch on this topic ... notice how the above comments use the term "bit mask" and "bitmasks") > */ > static bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r) > diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h > index 85ceaf9a31ac..c47ef2f13e8e 100644 > --- a/arch/x86/kernel/cpu/resctrl/internal.h > +++ b/arch/x86/kernel/cpu/resctrl/internal.h > @@ -492,6 +492,15 @@ union cpuid_0x10_3_eax { > unsigned int full; > }; > > +/* CPUID.(EAX=10H, ECX=ResID).ECX */ > +union cpuid_0x10_x_ecx { > + struct { > + unsigned int reserved:3; > + unsigned int noncont:1; > + } split; > + unsigned int full; > +}; > + > /* CPUID.(EAX=10H, ECX=ResID).EDX */ > union cpuid_0x10_x_edx { > struct { The core of the change looks good to me. Reinette