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The binding describes SoC-specific integration including clock and reset control for the USB subsystem. Signed-off-by: Adrian Ng Ho Yin --- .../bindings/usb/altr,agilex5-dwc3.yaml | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml diff --git a/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml b/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml new file mode 100644 index 000000000000..d40719e0e49d --- /dev/null +++ b/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/altr,agilex5-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera Agilex5 DWC3 USB SoC Controller Wrapper + +maintainers: + - Adrian Ng + +description: + The Altera Agilex5 SoCFPGA integrates a Synopsys DesignWare USB3 (DWC3) + controller that supports host, device and DRD modes. This binding describes + SoC integration including clocks, resets, PHY connections, and optional + IOMMU support. + +allOf: + - $ref: snps,dwc3-common.yaml# + +properties: + compatible: + const: altr,agilex5-dwc3 + + reg: + maxItems: 1 + + clocks: + items: + - description: Controller suspend clock + - description: Master/Core bus clock + + clock-names: + items: + - const: suspend_clk + - const: bus_clk + + interrupts: + maxItems: 1 + + phys: + items: + - description: USB2 PHY + - description: USB3 PHY + + phy-names: + items: + - const: usb2-phy + - const: usb3-phy + + iommus: + maxItems: 1 + + resets: + items: + - description: DWC3 core reset + - description: DWC3 ECC reset + + reset-names: + items: + - const: dwc3 + - const: dwc3-ecc + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - phys + - phy-names + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + usb31: usb@11000000 { + compatible = "altr,agilex5-dwc3"; + reg = <0x11000000 0x100000>; + interrupts = ; + clocks = <&clkmgr AGILEX5_USB31_SUSPEND_CLK>, + <&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>; + clock-names = "suspend_clk", "bus_clk"; + phys = <&usbphy0>, <&usbphy1>; + phy-names = "usb2-phy", "usb3-phy"; + resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; + reset-names = "dwc3", "dwc3-ecc"; + iommus = <&smmu 7>; + dr_mode = "host"; + }; -- 2.49.GIT