From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933956AbcHaNgk (ORCPT ); Wed, 31 Aug 2016 09:36:40 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:29489 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750708AbcHaNgj (ORCPT ); Wed, 31 Aug 2016 09:36:39 -0400 Subject: Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier To: Peter Zijlstra References: <1472640279-26593-1-git-send-email-matt.redfearn@imgtec.com> <1472640279-26593-7-git-send-email-matt.redfearn@imgtec.com> <20160831114847.GB10153@twins.programming.kicks-ass.net> CC: Ralf Baechle , , Adam Buchbinder , Arnd Bergmann , Masahiro Yamada , , "Michael S. Tsirkin" , Markos Chandras , Paul Burton From: Matt Redfearn Message-ID: <4c91d6c3-8141-594a-562c-96ea56776d2e@imgtec.com> Date: Wed, 31 Aug 2016 14:36:26 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: <20160831114847.GB10153@twins.programming.kicks-ass.net> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.150.130.83] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 31/08/16 12:48, Peter Zijlstra wrote: > On Wed, Aug 31, 2016 at 11:44:35AM +0100, Matt Redfearn wrote: >> Since R2 of the MIPS architecture, SYNC(0x10) has been an optional but >> architecturally defined ordering barrier. If a CPU does not implement it, >> the arch specifies that it must fall back to SYNC(0). >> >> Define the barrier type and always use it in the pm-cps code rather than >> falling back to the heavyweight sync(0) such that we can benefit from >> the lighter weight sync. >> > Changelog does not explain what 0x10 is, nor why its sufficient for this > case. Hi Peter, The code previously had 0x10 as a magic number, this patch just replaces that with a #defined name. The value is documented in the MIPS64 instruction set manual, https://imgtec.com/?do-download=4302, table 6.5. This sync type has been standard since MIPSr2. That document also states that "If an implementation does not use one of these non-zero values to define a different synchronization behavior, then that non-zero value of stype must act the same as stype zero completion barrier." As such, stype_ordering can always be set to this sync type rather than setting it only for certain CPUs. Thanks, Matt > > Changelog also fails to explain why you do this. > How do you expect anybody to review this?