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Peter Anvin" , Mario Limonciello , , Ariadne Conill , Sean Christopherson , "Juergen Gross" , , Ingo Molnar , References: <20261104013026.185392-1-jason.andryuk@amd.com> <20261104151820.GA716491@yaz-khff2.amd.com> Content-Language: en-US From: Jason Andryuk In-Reply-To: <20261104151820.GA716491@yaz-khff2.amd.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CE:EE_|CH3PR12MB7692:EE_ X-MS-Office365-Filtering-Correlation-Id: 162ac3d2-d68d-43cd-88cb-08df3a977510 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|23010399003|376014|7416014|1800799024|22082099003|18002099003|10067099003|261102123227099003|11063799006|5023799004|4143699003|261021123027099003|261026121527099003|261026140227099003|261022075727099003|261009223027099003|261028144727099003|261022105027099003|260925022911599003|261021121427099003|56012099006|260925021311599003|260925021911599003; X-Microsoft-Antispam-Message-Info: feS7RXoyVg7zwk3WxLJQHRx2/j8+vSmBO3tyDpIqw9d7pX52ciNCccC+PN2PhW7hzrv2yJlqCYevE27Sdv4mgVp0xx/4rk2+4+F15eAAoAywe52SMgGafiht9IxmATTaYWEhjinOofqyGwZ7znrD2eE2ECt7d8wc+xlM+kQ/zL8FLQLfzrQ7/irwfso8mqSRnkTwnpeipsAPdtFShFlvuH0RB1ZqvGfo2Qrm6GroOZjWuE8rtMMr0n7oaoj2feOhZh49P9ANIqTL5HAFfRb1tPR0BvekO1VBkFRvJ1U42F+cmcFeyy9N8MQ+GNdj73yVrI6x1mEt2+3/hpNL+VqS/stdnj3gocS8b4t868aHfHrfcQkVjNnhkQa6PcaYRlJfms0qggKbDf086dHBM9qqfTVDNwWqRfNXxY12VmJ4JvkyfOa0rZgDgbnqkAQFzV6++o6/Xu+iQg4cEBO5iktfeFNvs7HcXWS1Ctktt2OkmjpfDGrF+y6c814kq9g6NMdYTxwUCC5zwyMCJ/2VCa/XLaIa1qzxZwA+H3ACsiqLaTy9lSMlJ0KaH6Md8fpdCtJXr4NwN2NKTkiq9fsMvMurH5HU8oX2FESf7y1oBVyofEH8W+Xv5KZ26NpVGnWtRNIFuCRV/CVHeyy2SwLEnikUL83MMdyXq2ViBgjIjD0w1fI= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(23010399003)(376014)(7416014)(1800799024)(22082099003)(18002099003)(10067099003)(261102123227099003)(11063799006)(5023799004)(4143699003)(261021123027099003)(261026121527099003)(261026140227099003)(261022075727099003)(261009223027099003)(261028144727099003)(261022105027099003)(260925022911599003)(261021121427099003)(56012099006)(260925021311599003)(260925021911599003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: gRfP2mCEPcxlVCCDG86YObuTqFmaIhX9PDmGvHeX6rTEnMLgSPFMvRxnaCLgfSl3bGpQiOOWnPaGv6k+2BwLoNcX03nm1swSVmwwmFkNVljl20J0WWNV0dgyxo4QunCWxoZHpXsDd1yqqDYeinSjZc6Dtz3+Ex92hU6VuI4gE9mrfUbo+9fticZb/4lVu/l71spmawxM93UTjdW9O0hQdgHJcEe9XrlHHQa/5f7jPQr1uHOYeVMeIv+GOmHLlVppqON744K7o1BDh7PnhQzsrHpmCGV+KhS7i++SVQScwCzW6G6jq/Rub+fz2OqjLtOndgeYULvAQzyAgEch20pibpHpSlny8r4Sto+LQnLzbZkhT035mgvBZj+HSEh91zknVl0k4/teRXaiZK7RGSu5qKlAeRyXc4vL8Zj5gqA2ylnDylt4jrsvIgdBn1HCjrDp X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2026 17:17:08.6996 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 162ac3d2-d68d-43cd-88cb-08df3a977510 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7692 On 2026-11-04 10:18, Yazen Ghannam wrote: > On Tue, Nov 03, 2026 at 08:30:25PM -0500, Jason Andryuk wrote: >> print_s5_reset_status_mmio() expects to read FCH MMIO on baremetal. VMs >> don't have emulated FCH registers, so there is nothing to check. Add an >> early exit when running on a hypervisor. >> >> The real motivation is Xen PV domUs can't boot on Zen CPUs. PV domUs >> PTE contain system physical addresses - they don't have concept of guest >> physical addresses. domUs can only map physical addresses they are >> assigned, so a domU fails to map the FCH MMIO addresses. However >> set_pte() does not return failure, so ioremap() returns a pointer while >> the PTEs are unpopulated. print_s5_reset_status_mmio() faults when >> reading through the pointer, breaking the boot. This change fixes Xen >> PV domUs booting on Zen CPUs. >> >> dom0 can map the FCH MMIO, but it has X86_FEATURE_HYPERVISOR set. With >> this change, it no longer prints the reset reason. >> >> Fixes: ab8131028710 ("x86/CPU/AMD: Print the reason for the last reset") >> Cc: stable@vger.kernel.org >> Suggested-by: Borislav Petkov >> Signed-off-by: Jason Andryuk >> --- >> dom0 could work, but that would require a xen_initial_domain() check. >> >> I've wondered about a different approach: We can't directly check for a >> device for the FCH_PM_BASE memory, but maybe we could check for a PCI >> ISA Bridge with PCI_VENDOR_ID_AMD. That might be close enough to >> indicate real hardware? But it would still be a heuristic, so I'm not >> sure how much better that would be. > > Maybe, I had an older version that used the smbus device / i2c driver. > https://lore.kernel.org/all/20230407203720.18184-1-yazen.ghannam@amd.com/ > > Is this available in dom0? lspci shows 00:14.0 FCH SMBus Controller Kernel driver in use: piix4_smbus Kernel modules: i2c_piix4, sp5100_tco so, yes, it seems so. >> --- >> arch/x86/kernel/cpu/amd.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c >> index 40463bad1078..580ccc2ce5fc 100644 >> --- a/arch/x86/kernel/cpu/amd.c >> +++ b/arch/x86/kernel/cpu/amd.c >> @@ -1357,7 +1357,8 @@ static __init int print_s5_reset_status_mmio(void) >> u32 value; >> int i; >> >> - if (!cpu_feature_enabled(X86_FEATURE_ZEN)) >> + if (!cpu_feature_enabled(X86_FEATURE_ZEN) || >> + cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) >> return 0; >> >> addr = ioremap(FCH_PM_BASE + FCH_PM_S5_RESET_STATUS, sizeof(value)); >> -- > > Reviewed-by: Yazen Ghannam Thanks, Jason