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Fri, 5 Jul 2024 00:10:09 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.11.0-alpha0-566-g3812ddbbc-fm-20240627.001-g3812ddbb Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <4cfc5292-6f1a-4409-b229-2433e18f012f@app.fastmail.com> In-Reply-To: <9316cde1-26d0-54d5-43c3-1284288c685f@loongson.cn> References: <20240626063239.3722175-1-maobibo@loongson.cn> <79dcf093-614f-2737-bb03-698b0b3abc57@loongson.cn> <9c7d242e-660b-8d39-b69e-201fd0a4bfbf@loongson.cn> <059d66e4-dd5d-0091-01d9-11aaba9297bd@loongson.cn> <7e6a1dbc-779a-4669-4541-c5952c9bdf24@loongson.cn> <81dded06-ad03-9aed-3f07-cf19c5538723@loongson.cn> <0e28596c-3fe9-b716-b193-200b9b1d5516@loongson.cn> <554b10e8-a7ab-424a-f987-ea679859a220@loongson.cn> <01eb9efd-ca7a-4d4c-a29d-cfc2f6cfbb86@app.fastmail.com> <9316cde1-26d0-54d5-43c3-1284288c685f@loongson.cn> Date: Fri, 05 Jul 2024 12:09:49 +0800 From: "Jiaxun Yang" To: "Bibo Mao" , "Huacai Chen" Cc: "Tianrui Zhao" , "Xuerui Wang" , kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 2/3] LoongArch: KVM: Add LBT feature detection function Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable =E5=9C=A82024=E5=B9=B47=E6=9C=885=E6=97=A5=E4=B8=83=E6=9C=88 =E4=B8=8A=E5= =8D=8811:46=EF=BC=8Cmaobibo=E5=86=99=E9=81=93=EF=BC=9A > On 2024/7/5 =E4=B8=8A=E5=8D=8811:19, Jiaxun Yang wrote: >>=20 >>=20 >> =E5=9C=A82024=E5=B9=B47=E6=9C=885=E6=97=A5=E4=B8=83=E6=9C=88 =E4=B8=8A= =E5=8D=889:21=EF=BC=8Cmaobibo=E5=86=99=E9=81=93=EF=BC=9A >> [...] >>>> for you. >>> On the other hand, can you list benefits or disadvantage of approach= es >>> on different architecture? >>=20 >> So the obvious benefit of scratch vCPU would be maintaining consisten= cy and simpleness >> for UAPI. > I do not find the simpleness, for the same feature function, both VM=20 > feature and CPU feature is define as follows. Do you think it is for=20 > simple :) So they made a mistake here :-( We don't even need vCPU flag, just probing CPUCFG bits is sufficient. Note that in Arm's case, some CPU features have system dependencies, tha= t's why they need to be entitled twice. For us, we don't have such burden. If Arm doesn't set a good example here, please check RISC-V's CONFIG reg= on dealing ISA extensions. We don't even need such register because our CPUCFG can = perfectly describe ISA status. > > VM CAPBILITY: > KVM_CAP_ARM_PTRAUTH_ADDRESS > KVM_CAP_ARM_PTRAUTH_GENERIC > KVM_CAP_ARM_EL1_32BIT > KVM_CAP_ARM_PMU_V3 > KVM_CAP_ARM_SVE > KVM_CAP_ARM_PSCI > KVM_CAP_ARM_PSCI_0_2 > > CPU: > KVM_ARM_VCPU_POWER_OFF > KVM_ARM_VCPU_EL1_32BIT > KVM_ARM_VCPU_PSCI_0_2 > KVM_ARM_VCPU_PMU_V3 > KVM_ARM_VCPU_SVE > KVM_ARM_VCPU_PTRAUTH_ADDRESS > KVM_ARM_VCPU_PTRAUTH_GENERIC > KVM_ARM_VCPU_HAS_EL2 > > Also why scratch vcpu is created and tested on host cpu type rather th= an=20 > other cpu type? It wastes much time for host cpu type to detect capab= ility. To maximize supported features, on Arm there is KVM_ARM_VCPU_INIT ioctl. For us that's unnecessary, our kernel does not need to be aware of CPU t= ype, only CPUCFG bits are necessary. RISC-V is following the same convention. >>=20 >> It can also maximum code reuse probabilities in other user space hype= rvisor projects. >>=20 >> Also, it can benefit a potential asymmetrical system. I understand th= at it won't appear >> in near future, but we should always be prepared, especially in UAPI = design. > If for potential asymmetrical system, however there is only one scratc= h=20 > vcpu. is that right? how does only one scratch vcpu detect ASMP=20 > capability, and it is not bind to physical cpu to detect ASMP capabili= ty. > > In generic big.little is HMP rather than ASMP, are you agree. So I was talking about emulating asymmetrical guest. Each guest CPU shou= ld have it's own copy of properties. That's the lesson learnt. [...] Anyway I'm just trying to help out here, feel free to go ahead without t= aking my advice. I've seen so many pitfalls on all other arches and I don't want them to = repeat on LoongArch. But sometimes people only learn from mistakes. --=20 - Jiaxun