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([2a01:e0a:982:cbb0:8ad2:e64c:f150:ebc6]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434aa7e5e59sm30134885e9.44.2024.11.27.11.01.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Nov 2024 11:01:54 -0800 (PST) Message-ID: <4d237348-2128-479c-8122-b194ffb19e5c@linaro.org> Date: Wed, 27 Nov 2024 20:01:51 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: neil.armstrong@linaro.org Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH v2 04/11] drm/msm: adreno: add GMU_BW_VOTE feature flag To: Akhil P Oommen Cc: Viresh Kumar , Nishanth Menon , Stephen Boyd , "Rafael J. Wysocki" , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Connor Abbott , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org References: <20241119-topic-sm8x50-gpu-bw-vote-v2-0-4deb87be2498@linaro.org> <20241119-topic-sm8x50-gpu-bw-vote-v2-4-4deb87be2498@linaro.org> <20241123194316.yqvovktcptfep4dr@hu-akhilpo-hyd.qualcomm.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 27/11/2024 17:00, Akhil P Oommen wrote: > On 11/25/2024 1:46 PM, Neil Armstrong wrote: >> On 23/11/2024 20:43, Akhil P Oommen wrote: >>> On Tue, Nov 19, 2024 at 06:56:39PM +0100, Neil Armstrong wrote: >>>> The Adreno GMU Management Unit (GNU) can also scale the DDR Bandwidth >>>> along the Frequency and Power Domain level, but by default we leave the >>>> OPP core vote for the interconnect ddr path. >>>> >>>> While scaling via the interconnect path was sufficient, newer GPUs >>>> like the A750 requires specific vote paremeters and bandwidth to >>>> achieve full functionality. >>>> >>>> While the feature will require some data in a6xx_info, it's safer >>>> to only enable tested platforms with this flag first. >>>> >>>> Add a new feature enabling DDR Bandwidth vote via GMU. >>>> >>>> Signed-off-by: Neil Armstrong >>>> --- >>>>   drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + >>>>   1 file changed, 1 insertion(+) >>>> >>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/ >>>> drm/msm/adreno/adreno_gpu.h >>>> index >>>> 4702d4cfca3b58fb3cbb25cb6805f1c19be2ebcb..394b96eb6c83354ae008b15b562bedb96cd391dd 100644 >>>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h >>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h >>>> @@ -58,6 +58,7 @@ enum adreno_family { >>>>   #define ADRENO_FEAT_HAS_HW_APRIV        BIT(0) >>>>   #define ADRENO_FEAT_HAS_CACHED_COHERENT        BIT(1) >>>>   #define ADRENO_FEAT_PREEMPTION            BIT(2) >>>> +#define ADRENO_FEAT_GMU_BW_VOTE            BIT(3) >>> >>> Do we really need a feature flag for this? We have to carry this for >>> every >>> GPU going forward. IB voting is supported on all GMUs from A6xx GEN2 and >>> newer. So we can just check that along with whether the bw table is >>> dynamically generated or not. >> >> It depends on the bw table _and_ the a6xx_info.gmu table, I don't want to >> check both in all parts on the driver. >> > Thats fine then. Finally I converted the a6xx_info to a pointer, and it's fine checking this pointer instead of the quirk, since anyway we already check num_bws. Neil > > -Akhil. > >> Neil >> >>> >>> -Akhil >>> >>>>     /* Helper for formating the chip_id in the way that userspace >>>> tools like >>>>    * crashdec expect. >>>> >>>> -- >>>> 2.34.1 >>>> >> >> >