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Tue, 07 Oct 2025 21:41:47 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEbLgyaHnQnCYg1mkuvqGXZAuilnklbWsbGEyJCe1zpX8JiOQVqb233kzye9667JEzQiFkP2Q== X-Received: by 2002:a17:903:1b26:b0:248:e3fb:4dc8 with SMTP id d9443c01a7336-290272c045bmr26411785ad.39.1759898506997; Tue, 07 Oct 2025 21:41:46 -0700 (PDT) Received: from [10.218.42.132] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-28e8d125e9fsm183251915ad.36.2025.10.07.21.41.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 07 Oct 2025 21:41:46 -0700 (PDT) Message-ID: <4d586f0f-c336-4bf6-81cb-c7c7b07fb3c5@oss.qualcomm.com> Date: Wed, 8 Oct 2025 10:11:39 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/3] arm64: dts: qcom: sm8750: Add PCIe PHY and controller node To: Bjorn Andersson Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com References: <20250826-pakala-v3-0-721627bd5bb0@oss.qualcomm.com> <20250826-pakala-v3-2-721627bd5bb0@oss.qualcomm.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDA0MDAxOSBTYWx0ZWRfX2PmY9x+LAcsv v/WKdnIP4+beSEU7ZvztM7ejTu5OmJn+pN9j0OtwyydK3cK+LL17Y/wGooUfdAw4Cdr0z3ZfqEm yF+gV1BCrgwGBuXtyqSEfvDUm/fSOMmqNMfgAXbDK8uHFXzJ7rfPP2steDKrhMC0dBjSrXkWX0P /pM/ozMbHIQLpYy9zDKD17XNqwalUAjP8NX2EJNL7/Pyuj/2IA7Aa57ohFhvAQsu8QSTXMz/BgJ 0Dym6kam6dbQhsmfQf3RObkiVEl/kXbKZ35w2B7Mg703rv1iQObpgItfyAdmb7uGbDCFOk14imq tbYUW9cIGzF6XbTsOBDtmcOSqnqLXOzaV9KHY1rsSC/kp8RkvUr1BBNLTRo3iL+fQ9moqoMAvWv yElHuHFpKPUtkfpn2YYtns6sWlww9g== X-Authority-Analysis: v=2.4 cv=B6O0EetM c=1 sm=1 tr=0 ts=68e5eb8d cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=AkHrb9cOowbY_nbVBZgA:9 a=lTNlEBf13bCQAnnw:21 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: 18cuJq5yNFcKhBD_vfbJ-Ut4Esni405l X-Proofpoint-ORIG-GUID: 18cuJq5yNFcKhBD_vfbJ-Ut4Esni405l X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-07_02,2025-10-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 adultscore=0 impostorscore=0 spamscore=0 bulkscore=0 phishscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2510040019 On 10/2/2025 5:07 AM, Bjorn Andersson wrote: > On Tue, Aug 26, 2025 at 04:32:54PM +0530, Krishna Chaitanya Chundru wrote: >> Add PCIe controller and PHY nodes which supports data rates of 8GT/s >> and x2 lane. >> > > I tried to boot the upstream kernel (next-20250925 defconfig) on my > Pakala MTP with latest LA1.0 META and unless I disable &pcie0 the device > is crashing during boot as PCIe is being probed. > > Is this a known problem? Is there any workaround/changes in flight that > I'm missing? > Hi Bjorn, we need this fix for the PCIe to work properly. Please try it once. https://lore.kernel.org/all/20251008-sm8750-v1-1-daeadfcae980@oss.qualcomm.com/ - Krishna Chaitanya. > Regards, > Bjorn > >> Signed-off-by: Krishna Chaitanya Chundru >> --- >> arch/arm64/boot/dts/qcom/sm8750.dtsi | 180 ++++++++++++++++++++++++++++++++++- >> 1 file changed, 179 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi >> index 4643705021c6ca095a16d8d7cc3adac920b21e82..b47668a64bcead3e48f58eeb2e41c04660493cb7 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi >> @@ -631,7 +631,7 @@ gcc: clock-controller@100000 { >> clocks = <&bi_tcxo_div2>, >> <0>, >> <&sleep_clk>, >> - <0>, >> + <&pcie0_phy>, >> <0>, >> <0>, >> <0>, >> @@ -3304,6 +3304,184 @@ gic_its: msi-controller@16040000 { >> }; >> }; >> >> + pcie0: pcie@1c00000 { >> + device_type = "pci"; >> + compatible = "qcom,pcie-sm8750", "qcom,pcie-sm8550"; >> + reg = <0x0 0x01c00000 0x0 0x3000>, >> + <0x0 0x40000000 0x0 0xf1d>, >> + <0x0 0x40000f20 0x0 0xa8>, >> + <0x0 0x40001000 0x0 0x1000>, >> + <0x0 0x40100000 0x0 0x100000>, >> + <0x0 0x01C03000 0x0 0x1000>; >> + reg-names = "parf", >> + "dbi", >> + "elbi", >> + "atu", >> + "config", >> + "mhi"; >> + >> + #address-cells = <3>; >> + #size-cells = <2>; >> + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, >> + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x23d00000>, >> + <0x03000000 0x4 0x00000000 0x4 0x00000000 0x3 0x00000000>; >> + bus-range = <0x00 0xff>; >> + >> + dma-coherent; >> + >> + linux,pci-domain = <0>; >> + >> + msi-map = <0x0 &gic_its 0x1400 0x1>, >> + <0x100 &gic_its 0x1401 0x1>; >> + msi-map-mask = <0xff00>; >> + >> + num-lanes = <2>; >> + >> + interrupts = , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + ; >> + interrupt-names = "msi0", >> + "msi1", >> + "msi2", >> + "msi3", >> + "msi4", >> + "msi5", >> + "msi6", >> + "msi7", >> + "global"; >> + >> + #interrupt-cells = <1>; >> + interrupt-map-mask = <0 0 0 0x7>; >> + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, >> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, >> + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, >> + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, >> + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, >> + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, >> + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, >> + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; >> + clock-names = "aux", >> + "cfg", >> + "bus_master", >> + "bus_slave", >> + "slave_q2a", >> + "ddrss_sf_tbu", >> + "noc_aggr", >> + "cnoc_sf_axi"; >> + >> + interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "pcie-mem", >> + "cpu-pcie"; >> + >> + iommu-map = <0x0 &apps_smmu 0x1400 0x1>, >> + <0x100 &apps_smmu 0x1401 0x1>; >> + >> + resets = <&gcc GCC_PCIE_0_BCR>; >> + reset-names = "pci"; >> + >> + power-domains = <&gcc GCC_PCIE_0_GDSC>; >> + >> + operating-points-v2 = <&pcie0_opp_table>; >> + >> + status = "disabled"; >> + >> + pcie0_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + /* GEN 1 x1 */ >> + opp-2500000 { >> + opp-hz = /bits/ 64 <2500000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + opp-peak-kBps = <250000 1>; >> + }; >> + >> + /* GEN 1 x2 and GEN 2 x1 */ >> + opp-5000000 { >> + opp-hz = /bits/ 64 <5000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + opp-peak-kBps = <500000 1>; >> + }; >> + >> + /* GEN 2 x2 */ >> + opp-10000000 { >> + opp-hz = /bits/ 64 <10000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + opp-peak-kBps = <1000000 1>; >> + }; >> + >> + /* GEN 3 x1 */ >> + opp-8000000 { >> + opp-hz = /bits/ 64 <8000000>; >> + required-opps = <&rpmhpd_opp_nom>; >> + opp-peak-kBps = <984500 1>; >> + }; >> + >> + /* GEN 3 x2 */ >> + opp-16000000 { >> + opp-hz = /bits/ 64 <16000000>; >> + required-opps = <&rpmhpd_opp_nom>; >> + opp-peak-kBps = <1969000 1>; >> + }; >> + >> + }; >> + >> + pcieport0: pcie@0 { >> + device_type = "pci"; >> + reg = <0x0 0x0 0x0 0x0 0x0>; >> + bus-range = <0x01 0xff>; >> + >> + #address-cells = <3>; >> + #size-cells = <2>; >> + ranges; >> + phys = <&pcie0_phy>; >> + }; >> + }; >> + >> + pcie0_phy: phy@1c06000 { >> + compatible = "qcom,sm8750-qmp-gen3x2-pcie-phy"; >> + reg = <0 0x01c06000 0 0x2000>; >> + >> + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, >> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, >> + <&tcsrcc TCSR_PCIE_0_CLKREF_EN>, >> + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, >> + <&gcc GCC_PCIE_0_PIPE_CLK>; >> + clock-names = "aux", >> + "cfg_ahb", >> + "ref", >> + "rchng", >> + "pipe"; >> + >> + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; >> + assigned-clock-rates = <100000000>; >> + >> + resets = <&gcc GCC_PCIE_0_PHY_BCR>; >> + reset-names = "phy"; >> + >> + power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>; >> + >> + #clock-cells = <0>; >> + clock-output-names = "pcie0_pipe_clk"; >> + >> + #phy-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> ufs_mem_phy: phy@1d80000 { >> compatible = "qcom,sm8750-qmp-ufs-phy"; >> reg = <0x0 0x01d80000 0x0 0x2000>; >> >> -- >> 2.34.1 >>