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[91.159.24.186]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5bff9a660b0sm485831e87.11.2026.11.05.07.39.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Nov 2026 07:39:09 -0800 (PST) Message-ID: <4d656385-fd3b-426d-b326-b1d20ba1e2d7@linaro.org> Date: Thu, 5 Nov 2026 17:39:09 +0200 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] dt-bindings: media: qcom,glymur-camss: Use CSIPHY indices for ports To: Loic Poulain , Krzysztof Kozlowski Cc: Nihal Kumar Gupta , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Suresh Vankadara , Vikram Sharma References: <20261102-glymur_camss-v1-0-fcb619fc7319@oss.qualcomm.com> <20261102-glymur_camss-v1-1-fcb619fc7319@oss.qualcomm.com> <20261104-real-nebulous-ostrich-017e92@quoll> <72064a9a-1b2e-4c24-99e2-2cc15a8dd7f1@oss.qualcomm.com> <539842db-c672-4549-b861-4a6f3be47556@oss.qualcomm.com> <1db9bf48-01d8-44fe-8dd2-7a3c84ecc556@kernel.org> <62fba00d-831c-44cc-8d3e-083a95abfbe8@kernel.org> From: Vladimir Zapolskiy In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 11/5/26 16:01, Loic Poulain wrote: > On Thu, Nov 5, 2026 at 2:21 PM Krzysztof Kozlowski wrote: >> >> On 05/11/2026 13:04, Loic Poulain wrote: >>> On Thu, Nov 5, 2026 at 11:45 AM Krzysztof Kozlowski wrote: >>>> >>>> On 05/11/2026 10:53, Loic Poulain wrote: >>>>> So some chipsets share the same IP blocks, with some block/phy >>>>> instances disabled. As a result, we need to decide whether we're >>>>> numbering based on active instances or on the actual hardware instance >>>>> index/offset. If we use active-instance numbering, then yes, it should >>>>> be @2 (CSIPHY4 being the third active instance). Alternatively, if the >>>>> port numbering is intended to reflect the hardware instance offset, >>>>> matching the register prop, then @4 would be more appropriate. It also >>>>> has the advantage of directly identifying the underlying hardware >>>>> instance, without requiring any additional driver-side mapping. In any >>>>> case, @3 is incorrect. >>>>> >>>>> That said, since the bindings have already been merged in its current >>>>> form, we'll need to preserve backward compatibility when addressing >>>>> this. >>>> >>>> This is the input port to camss, so how is it called in camss, not the >>>> csi phy? >>> >>> The CSIPHYs are connected to the CAMSS input ports, which can then be >>> multiplexed and routed to different CSIDs. The mux identifies its PHY >>> inputs using the hardware PHY IDs, so the CSIPHY4 is identified as the >>> CAMSS PHY4 input. In this configuration, PHY2 and PHY3 inputs are not >>> connected. >> >> I could not find that information in Glymur HPG, but maybe I looked >> wrong. CSID Wrapper lists CSID 0-2, not 0, 1 and 4, but again maybe I am >> looking at wrong device description/interface... > > Yes, there are three CSIDs (CSID0-2) and two CSID_LITEs > (CSID_LITE0-1). These blocks select the PHY source to be routed by > programming their PHY ID (PHY ID = PHY index + 1), as defined by the > PHY_NUM_SEL field in CSI2_RX_CFG0. > > If the CAMSS port ID matches the PHY index, the port ID can be used > directly as a routing reference, which keeps the implementation > straightforward. > > Alternatively, exposing logical port IDs such as { 0, 1, 2 } also > makes sense. In that case, the driver would simply maintain an > internal mapping table, for example mapping DT/logical ports { 0, 1, 2 > } to PHY indices { 0, 1, 4 }. As long as we establish and document the > convention, either approach should work fine. > > Today, the Glymur bindings define DT ports { 0, 1, 3 } to map to PHY > indices { 0, 1, 4 }. One could argue that this is already an > established convention, as it is documented in the bindings. However, > it is somewhat confusing. > I believe it should be fine to have incontiguous port indices, because there is no need to link unused phys to CAMSS on any particular board, therefore there will be unavoidable "holes", and this can be set right in the documentation of CSIPHY to CAMSS connection. -- Best wishes, Vladimir