Re: [PATCH v11 00/74] Add HDMI 2.0 support to DW HDMI QP TX

[Robin Räber <robin.raebi@gmail.com>]

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Hi Cristian,

I tested this series on a Xunlong Orange Pi 5 (RK3588S) driving an
AOC Q32G1WG4 monitor (2560x1440@144, TMDS char rate 592 MHz) and can
report that scrambling works, with one interop issue described below.

A note on the test base: drm-misc-next at the series' base commit does
not boot on this board for reasons unrelated to the series (the
unpatched base commit hangs early as well; I can dig into that
separately). I therefore backported the series onto v7.2.3, dropping
the vc4/sun4i/tests patches and adjusting for minor context drift in
drm_connector.c and the scdc/hdmi helpers. The dw-hdmi-qp, rockchip,
bridge_connector and helper patches applied without functional
changes.

With the backport applied, all four 2560x1440 modes (60/100/120/144)
are exposed and 144 Hz works, but scrambling initially failed:

  rockchip-drm display-subsystem: [drm] Sink doesn't support scrambling.
  dwhdmiqp-rockchip fde80000.hdmi: Failed to enable scrambling: -22

The cause is the monitor's EDID: its HF-VSDB declares a Maximum TMDS
Character Rate of 600 MHz but leaves the SCDC Present flag unset, so
drm_scdc_sink_supports_scrambling() rejects it. The SCDC interface of
this display is nevertheless fully functional: reading SCDC via DDC
returns sink version 1, writes are accepted, and after the change
below TMDS_CONFIG reads back 0x03 (scrambling + 40-bit clock ratio)
with a stable picture at 592 MHz.

Since HDMI 2.0 mandates SCDC support for character rates above
340 MHz, I worked around it by trusting the declared rate:

--- a/drivers/gpu/drm/display/drm_hdmi_helper.c
+++ b/drivers/gpu/drm/display/drm_hdmi_helper.c
@@ static bool drm_scdc_sink_supports_scrambling(struct drm_connector *connector)
 {
 	const struct drm_display_info *info = &connector->display_info;
 
-	return info->is_hdmi &&
-	       info->hdmi.scdc.supported &&
-	       info->hdmi.scdc.scrambling.supported;
+	if (!info->is_hdmi)
+		return false;
+
+	/*
+	 * Some displays (e.g. AOC Q32G1WG4) declare a Max TMDS Character
+	 * Rate above 340 MHz in their HF-VSDB but leave the SCDC Present
+	 * flag unset, even though SCDC is functional. The spec mandates
+	 * SCDC support for rates above 340 MHz, so trust the declared rate.
+	 */
+	if (info->max_tmds_clock > 340000)
+		return true;
+
+	return info->hdmi.scdc.supported &&
+	       info->hdmi.scdc.scrambling.supported;
 }

I'm happy to test further revisions on this hardware, and to submit
the above as a proper patch if you think this is the right place to
handle such non-conformant EDIDs.

For the dw-hdmi-qp/rockchip/helper parts, on the backport described
above:

Tested-by: Robin Räber <robin.raebi@gmail.com>

Best regards,
Robin