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Mon, 03 Feb 2025 09:28:09 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5139S98P001452 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 3 Feb 2025 09:28:09 GMT Received: from [10.216.21.39] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 3 Feb 2025 01:28:01 -0800 Message-ID: <4dab19d0-22eb-2395-56fd-758c3c0d8bc7@quicinc.com> Date: Mon, 3 Feb 2025 14:57:58 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v9 00/28] Qualcomm iris video decoder driver Content-Language: en-US To: Johan Hovold , Stefan Schmidt CC: Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Philipp Zabel , "Hans Verkuil" , Sebastian Fricke , Bryan O'Donoghue , Dmitry Baryshkov , Neil Armstrong , Nicolas Dufresne , =?UTF-8?Q?Uwe_Kleine-K=c3=b6nig?= , Jianhua Lu , , , , , "Krzysztof Kozlowski" , Vedang Nagar , Bjorn Andersson References: <20241212-qcom-video-iris-v9-0-e8c2c6bd4041@quicinc.com> From: Vikash Garodia In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: tvZEWs4jbm0pUGZUtl8u2I2gNHwiYjP4 X-Proofpoint-ORIG-GUID: tvZEWs4jbm0pUGZUtl8u2I2gNHwiYjP4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-03_04,2025-01-31_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 mlxlogscore=999 impostorscore=0 bulkscore=0 malwarescore=0 clxscore=1015 adultscore=0 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502030074 On 2/3/2025 2:13 PM, Johan Hovold wrote: > On Wed, Jan 22, 2025 at 04:34:51PM +0100, Stefan Schmidt wrote: >> On Thu, 9 Jan 2025 at 15:58, Johan Hovold wrote: >>> On Thu, Dec 12, 2024 at 05:21:22PM +0530, Dikshita Agarwal wrote: > >>>> Introduce support for Qualcomm new video acceleration hardware i.e. >>>> iris, used for video stream decoding. >>> >>>> Note: A harmless onetime error log "Lucid PLL latch failed. Output may >>>> be unstable!" is seen during bootup. It doesn't impact any video >>>> usecase and is currently under discussion. >>> >>> This could be an indication that some resources are not described >>> correctly and could potentially require both binding and driver changes >>> to address. >>> >>> This is also something which could cause trouble later (e.g. during >>> suspend) even if you manage to get the clock running after boot. >>> >>> Generally, you should not be introducing any new warnings; they are >>> there to let you know that something is wrong. >>> >>> Where is this issue being discussed? >>> >>> I think we at least need a public analysis and understanding of the >>> problem before merging this. >> >> Taniya Das proposed a patchset to reconfigure PLL in the clk-alpha-pll >> which allows the videocc-sm8550 driver to configure it correctly. >> https://lore.kernel.org/linux-arm-msm/20250113-support-pll-reconfigure-v1-0-1fae6bc1062d@quicinc.com/T/ >> >> I tested the Iris driver with this patchset and I am no longer seeing >> the Lucid PLL latch failed warning. > > Thanks for the pointer. Please make sure to reference this series (and > summarise the underlying issue) when resending this series. > > Judging from a quick look the approach taken there seems like a bit of a > hack so it may not get merged in its current form. IIUC fixing the PLL > issue properly may depend on adding support for multiple power domains > to the clock drivers. It would be good if you can add your comment to the PLL fix series [1] so that the patch owner can discuss on your suggestion. Regards, Vikash [1] https://lore.kernel.org/linux-arm-msm/20250113-support-pll-reconfigure-v1-0-1fae6bc1062d@quicinc.com/T/