From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6676EEE4993 for ; Mon, 21 Aug 2023 15:08:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235812AbjHUPIX convert rfc822-to-8bit (ORCPT ); Mon, 21 Aug 2023 11:08:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231829AbjHUPIW (ORCPT ); Mon, 21 Aug 2023 11:08:22 -0400 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 2A529BC; Mon, 21 Aug 2023 08:08:19 -0700 (PDT) Authenticated-By: X-SpamFilter-By: ArmorX SpamTrap 5.77 with qID 37LF7WwyC031950, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (rtexh36505.realtek.com.tw[172.21.6.25]) by rtits2.realtek.com.tw (8.15.2/2.81/5.90) with ESMTPS id 37LF7WwyC031950 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 21 Aug 2023 23:07:32 +0800 Received: from RTEXDAG02.realtek.com.tw (172.21.6.101) by RTEXH36505.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.32; Mon, 21 Aug 2023 23:07:54 +0800 Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by RTEXDAG02.realtek.com.tw (172.21.6.101) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.7; Mon, 21 Aug 2023 23:07:53 +0800 Received: from RTEXMBS04.realtek.com.tw ([fe80::e138:e7f1:4709:ff4d]) by RTEXMBS04.realtek.com.tw ([fe80::e138:e7f1:4709:ff4d%5]) with mapi id 15.01.2375.007; Mon, 21 Aug 2023 23:07:53 +0800 From: Justin Lai To: Andrew Lunn CC: "kuba@kernel.org" , "davem@davemloft.net" , "edumazet@google.com" , "pabeni@redhat.com" , "linux-kernel@vger.kernel.org" , "netdev@vger.kernel.org" Subject: RE: [PATCH net-next v3 1/2] net/ethernet/realtek: Add Realtek automotive PCIe driver code Thread-Topic: [PATCH net-next v3 1/2] net/ethernet/realtek: Add Realtek automotive PCIe driver code Thread-Index: AQHZz4Ya38d07ViN20S7bf3O9T4Qta/q9pcAgAMgk2D//87KAIABzfpQ///CfgCABJnu0IAALOEAgACljtA= Date: Mon, 21 Aug 2023 15:07:53 +0000 Message-ID: <4db3248874d64418b63fdf5c5e8a0f79@realtek.com> References: <20230815143756.106623-1-justinlai0215@realtek.com> <20230815143756.106623-2-justinlai0215@realtek.com> <95f079a4-19f9-4501-90d9-0bcd476ce68d@lunn.ch> <4955506dbf6b4ebdb67cbb738750fbc8@realtek.com> <4951391892534eaeb2da96f052364e4c@realtek.com> <4b630aeb-3098-4108-b8dc-7da6e55a7cf1@lunn.ch> <6d35d56f78b7452b9330c3257748fa3c@realtek.com> <97f3744d-afbf-4562-9168-5b9e211fac1f@lunn.ch> In-Reply-To: <97f3744d-afbf-4562-9168-5b9e211fac1f@lunn.ch> Accept-Language: zh-TW, en-US Content-Language: zh-TW X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.21.210.185] x-kse-serverinfo: RTEXDAG02.realtek.com.tw, 9 x-kse-antispam-interceptor-info: fallback x-kse-antivirus-interceptor-info: fallback Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-ServerInfo: RTEXH36505.realtek.com.tw, 9 X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-Antivirus-Interceptor-Info: fallback X-KSE-AntiSpam-Interceptor-Info: fallback Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > Sorry, please allow me to explain again. > > The RTL90xx Series supports I2C, MDC/MDIO and SPI slave to access the > registers of Ethernet Switch Core and the external CPU could manage it via > these pins. > > I was wondering if you had mis-understood my question. The bus 'master' is > the device which controls the bus. SPI and MDIO has one bus master, and there > can be multiple clients on the bus. I2C in theory can have multiple bus masters > on one bus, bit it is not done too often. Your switch is a client. > > So my question was, are the bus masters also on PCIE enpoints within the chip. > From an architecture standpoint, it would make sense they are, all you need is > one 4x PCIE slot, and this chip gives you everything you need. But you can also > make use of the SoCs I2C, SPI or MDIO bus. > > Andrew Thanks, I understand what you mean. But I2C, SPI, MDIO are connected to the SoC through this chip's external pins, not on the PCIe bus. Actually, there is the other function in the PCIe GMAC(Multiple function) to manage the registers of Switch Core. Should they be integrated into the MFD driver? Not everyone will use this function.