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micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="=-szCbYoUqh7Wz+RUvwIxJ" Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: impulsing.ch X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: ZR1P278MB1137.CHEP278.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-Network-Message-Id: cf6678a5-ce9c-4595-9418-08de281a3be0 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2025 09:50:27.1419 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 86709429-7470-4d0c-bd3c-b912eebdee40 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: WCbMMO/E3fIC3Yp4qo2XxHBYze+Mnz/kYHtalx7ZU6R4fk1CEh3Ur8TTWRa4JtFymuxF1XTZRvaYjSXhonFXofT0ZzIj1mitP4dMjWBPrlA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PPF666B94A1D --=-szCbYoUqh7Wz+RUvwIxJ Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2025-11-19 at 19:40 +0100, Herve Codina wrote: > Hi Luca, Francesco, others >=20 > On Wed, 19 Nov 2025 18:27:38 +0100 > "Luca Ceresoli" wrote: >=20 > > Hello, > >=20 > > On Wed Nov 19, 2025 at 1:24 PM CET, Francesco Dolcini wrote: > > ... > > > > I might be mistaken, but I don't think the PLL will work if > > > > unlocked... > > > > But maybe the case is that it unlocks and lock again right > > > > afterwards.=C2=A0=20 > > > > > > Jo=C3=A3o, Francesco, on what hardware do you observe the > > > > > > problem? Which SoC? > > > > > > Which encoder, any previous bridges?=C2=A0=20 > > > > >=20 > > > > > Verdin AM62, TI AM62 SOC, arch/arm64/boot/dts/ti/k3-am62- > > > > > verdin.dtsi > > > > >=20 > > > > > There is a DPI to DSI bridge in the module, tc358778, it has > > > > > a 25MHz > > > > > reference clock. > > > > >=20 > > > > > TI AM62 DPI -> Toshiba TC358768 DSI -> TI SN65DSI83 -> > > > > > Display > > > > >=20 > > > > > From a preliminary investigation this is a HW limitation, we > > > > > are not > > > > > able to generate a "good enough" DSI clock, see > > > > > tc358768_calc_pll() for=C2=A0=20 > >=20 > > Thanks Francesco for the feedback! > >=20 > > I'm not sure I completely understand the issue described, but if > > the TI > > bridge requires a clock that cannot be provided by the hardware, > > then this > > actually looks like "a HW limitation" as you wrote, due to a HW > > integration > > limitation/bug/issue/whatever. In case this is confirmed, I think > > quirks > > are an appropriate tool to handle HW integration issues. > >=20 > > > > I haven't studied the docs or done any testing, but I would > > > > think that > > > > it doesn't matter for the PLL even if the incoming DSI clock is > > > > a bit > > > > off, as long as it's continuous and stable. > > > >=20 > > > > My first thought was that the DSI is using non-continuous > > > > clock, but at > > > > least the driver has code to drop the > > > > MIPI_DSI_CLOCK_NON_CONTINUOUS flag. > > > > =C2=A0 > > > > > the actual code implementation of it, I believe that the > > > > > datasheet is > > > > > not available without NDA. > > > > >=20 > > > > > Maybe the ugly hack "works-without-pll" is the way to work? > > > > > It will > > > > > require a DT change, but this seems doable.=C2=A0=20 > > > >=20 > > > > Revert is easier than adding new hacky DT properties... At > > > > least until > > > > the problem is understood. > > > > =C2=A0 > > > > > Please note that this is the outcome of a short investigation > > > > > done > > > > > yesterday afternoon, so maybe I am overlooking something, > > > > > unfortunately > > > > > I do not have the bandwidth to work on it more this week. > > > > > =C2=A0 > > > > > > Which clock rates?=C2=A0=20 > > > > > 71100000=C2=A0=20 > > > > It would be a good test to try out with a few different > > > > clocks.=C2=A0=20 > > >=20 > > > 50 MHz works, for example. > > >=20 > > > It seems that the issue exists when the actual display clock is > > > different > > > from the dsi clock. And this can happen for the reason I > > > explained > > > before (the DSI clock is computed starting from this 25MHz > > > reference > > > clock).=C2=A0=20 > >=20 >=20 > If there is no way to set a correct clock, I agree with Luca a quirk > should > be the best solution. >=20 > For instance, in the dts: > =C2=A0 ti,pll_may_unlock_quirk; I followed the discussion only loosely. But I once worked on bringing up the SN65DSI83 and from what I can remember is that there was a frequency range of the input clock where the PLL of SN65DSI83 just did not lock at all. I couldn't explain what was happening since the clock I fed was within the limits of the documentation I had. What I ultimately did was to just choose a clock that works. Given that experience I'm not sure about adding quirks on TI side. But anyway I'm not very familiar with the topic and it's a long time since I worked on it. Just wanted to point out this experience I had, maybe it helps. Best Regards, Philippe >=20 > In the driver, mask the PLL unlock status bit from monitoring > (polling > and irq) if this boolean property is true: > =C2=A0- Mask IRQ PLL Unlock bit in REG_IRQ_EN when IRQ are enabled > =C2=A0- Mask IRQ PLL Unlock bit in REG_IRQ_STAT in > sn65dsi83_handle_errors() to > =C2=A0=C2=A0 avoid a recover process on PLL unlock. >=20 > Best regards, > Herv=C3=A9 --=-szCbYoUqh7Wz+RUvwIxJ Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: quoted-printable -----BEGIN PGP SIGNATURE-----=0A= =0A= iQHTBAABCgA9FiEEPaCxfVqqNYSPnRhRjRDjR2hoXxoFAmke5DcfHHBoaWxpcHBl=0A= LnNjaGVua2VyQGltcHVsc2luZy5jaAAKCRCNEONHaGhfGiQBDADL/Tx/Lfedv4WA=0A= Ya18XLBvAuUH8LkyJ/B/Oi2SjIcpBrP/GZJyZjn+fyK1vEaYV8HUrI4leaBCVzrF=0A= l6tYd9oTHwM/E41o5zS9jraf+B6Fbha5pu9Nyi6xGvntXFFPatGKGdD03IPvxTzH=0A= UHg3KsvBLC24HwxsZCvwj6DnMi5gV4eXkNIWfLnbR2jKhq+UwVg0iAVtJjVLlwdt=0A= pfZvUyZcjMr9cKS35A6Wdm/7dpcVvaE2+MwRVyi//q7RwPFSPiKj6pLeQVgRJFDR=0A= rZgu0qolvg1HAcVs3vp76hVQLJLPnfVD+Gewff29HIu2zKF70sSGtGho4K8paqkn=0A= qFZdzia8Xn40teb+a5v2+F1/8z0qUo7rRyNe6cy9VBIsuYLhxKnHG/ESgDPLYJTl=0A= 0w/dD7h6BRB+LJ/hlm669zYdHyq2lVWmNnCiJVf3jPSz0LUpWJ7d2tUFH2PWZAnK=0A= Gz/2iiVzUtKUtQfo39KNYwO4X6MNcM762gTTIVPtDx/KkjpzGQM=3D=0A= =3D7Dq+=0A= -----END PGP SIGNATURE-----=0A= --=-szCbYoUqh7Wz+RUvwIxJ--