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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-acaa1ccc2dcsm427286966b.132.2025.04.11.03.52.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 11 Apr 2025 03:52:35 -0700 (PDT) Message-ID: <4e265348-3466-49fb-82e2-255205052d1e@oss.qualcomm.com> Date: Fri, 11 Apr 2025 12:52:32 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/4] Retrieve information about DDR from SMEM To: Dmitry Baryshkov , Konrad Dybcio Cc: Konrad Dybcio , Bjorn Andersson , Kees Cook , "Gustavo A. R. Silva" , Rob Clark , Sean Paul , Abhinav Kumar , David Airlie , Simona Vetter , Dmitry Baryshkov , Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org References: <20250409-topic-smem_dramc-v1-0-94d505cd5593@oss.qualcomm.com> <685e784c-3f36-4cd1-9c34-7f98c64d50f2@oss.qualcomm.com> <0bec3e62-0753-4c3d-abe1-1a43356afc80@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: NZMhn1nuPijSj6Esp0yHNoULfDeCjmmc X-Proofpoint-GUID: NZMhn1nuPijSj6Esp0yHNoULfDeCjmmc X-Authority-Analysis: v=2.4 cv=NaLm13D4 c=1 sm=1 tr=0 ts=67f8f475 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=E-cWInRRfnsFT7zTJZEA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-11_04,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 impostorscore=0 priorityscore=1501 adultscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=443 clxscore=1015 phishscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504110068 On 4/11/25 12:50 PM, Dmitry Baryshkov wrote: > On Fri, Apr 11, 2025 at 12:03:03PM +0200, Konrad Dybcio wrote: >> On 4/11/25 11:57 AM, Dmitry Baryshkov wrote: >>> On Fri, 11 Apr 2025 at 12:49, Konrad Dybcio >>> wrote: >>>> >>>> On 4/9/25 5:49 PM, Konrad Dybcio wrote: >>>>> On 4/9/25 5:44 PM, Dmitry Baryshkov wrote: >>>>>> On 09/04/2025 17:47, Konrad Dybcio wrote: >>>>>>> SMEM allows the OS to retrieve information about the DDR memory. >>>>>>> Among that information, is a semi-magic value called 'HBB', or Highest >>>>>>> Bank address Bit, which multimedia drivers (for hardware like Adreno >>>>>>> and MDSS) must retrieve in order to program the IP blocks correctly. >>>>>>> >>>>>>> This series introduces an API to retrieve that value, uses it in the >>>>>>> aforementioned programming sequences and exposes available DDR >>>>>>> frequencies in debugfs (to e.g. pass to aoss_qmp debugfs). More >>>>>>> information can be exposed in the future, as needed. >>>>>> >>>>>> I know that for some platforms HBB differs between GPU and DPU (as it's being programmed currently). Is there a way to check, which values are we going to program: >>>>>> >>>>>> - SM6115, SM6350, SM6375 (13 vs 14) >>>> >>>> SM6350 has INFO_V3 >>>> SM6375 has INFO_V3_WITH_14_FREQS >>> >>> I'm not completely sure what you mean here. I pointed out that these >>> platforms disagreed upon the HBB value between the DPU/msm_mdss.c and >>> a6xx_gpu.c. >>> In some cases (a610/SM6115 and a619/SM6350) that was intentional to >>> fix screen corruption issues. I don't remember if it was the case for >>> QCM2290 or not. >> >> As I said below, I couldn't get a good answer yet, as the magic value >> is not provided explicitly and I'll hopefully be able to derive it from >> the available data > > I see... > Is this data even supposed to be poked into? The foo_WITH_bar types > doesn't sound like a very stable API. Yeah, it was designed with both the producer and consumer being part of a single codebase, always having the data structures in sync.. Konrad