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([2001:b07:6468:f312:7848:99b4:482a:e888]) by smtp.gmail.com with ESMTPSA id u5sm21556158wrp.81.2020.03.24.04.20.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Mar 2020 04:20:32 -0700 (PDT) Subject: Re: [PATCH v3 34/37] KVM: nVMX: Don't flush TLB on nested VMX transition To: Sean Christopherson Cc: Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Ben Gardon , Junaid Shahid , Liran Alon , Boris Ostrovsky , John Haxby , Miaohe Lin , Tom Lendacky References: <20200320212833.3507-1-sean.j.christopherson@intel.com> <20200320212833.3507-35-sean.j.christopherson@intel.com> From: Paolo Bonzini Message-ID: <4e2b2b82-278e-72d9-4db3-5047b678049c@redhat.com> Date: Tue, 24 Mar 2020 12:20:31 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <20200320212833.3507-35-sean.j.christopherson@intel.com> Content-Type: text/plain; charset=windows-1252 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 20/03/20 22:28, Sean Christopherson wrote: > Unconditionally skip the TLB flush triggered when reusing a root for a > nested transition as nested_vmx_transition_tlb_flush() ensures the TLB > is flushed when needed, regardless of whether the MMU can reuse a cached > root (or the last root). > > Signed-off-by: Sean Christopherson So much for my WARN_ON. :) Paolo > --- > arch/x86/kvm/mmu/mmu.c | 2 +- > arch/x86/kvm/vmx/nested.c | 6 ++++-- > 2 files changed, 5 insertions(+), 3 deletions(-) > > diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c > index 84e1e748c2b3..7b0fb7f2c24d 100644 > --- a/arch/x86/kvm/mmu/mmu.c > +++ b/arch/x86/kvm/mmu/mmu.c > @@ -5038,7 +5038,7 @@ void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly, > kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty, > execonly, level); > > - __kvm_mmu_new_cr3(vcpu, new_eptp, new_role.base, false, true); > + __kvm_mmu_new_cr3(vcpu, new_eptp, new_role.base, true, true); > > if (new_role.as_u64 == context->mmu_role.as_u64) > return; > diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c > index db3ce8f297c2..92aab4166498 100644 > --- a/arch/x86/kvm/vmx/nested.c > +++ b/arch/x86/kvm/vmx/nested.c > @@ -1161,10 +1161,12 @@ static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool ne > } > > /* > - * See nested_vmx_transition_mmu_sync for details on skipping the MMU sync. > + * Unconditionally skip the TLB flush on fast CR3 switch, all TLB > + * flushes are handled by nested_vmx_transition_tlb_flush(). See > + * nested_vmx_transition_mmu_sync for details on skipping the MMU sync. > */ > if (!nested_ept) > - kvm_mmu_new_cr3(vcpu, cr3, false, > + kvm_mmu_new_cr3(vcpu, cr3, true, > !nested_vmx_transition_mmu_sync(vcpu)); > > vcpu->arch.cr3 = cr3; >