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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af63589cab0sm728955766b.38.2025.07.30.04.57.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Jul 2025 04:57:07 -0700 (PDT) Message-ID: <4e9ec735-1278-4475-8898-1e12ccb94909@oss.qualcomm.com> Date: Wed, 30 Jul 2025 13:57:03 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next v5 03/14] net: ethernet: qualcomm: Add PPE driver for IPQ9574 SoC To: Luo Jie , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lei Wei , Suruchi Agarwal , Pavithra R , Simon Horman , Jonathan Corbet , Kees Cook , "Gustavo A. R. Silva" , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-hardening@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com References: <20250626-qcom_ipq_ppe-v5-0-95bdc6b8f6ff@quicinc.com> <20250626-qcom_ipq_ppe-v5-3-95bdc6b8f6ff@quicinc.com> <4556893f-982b-435d-aed1-d661ee31f862@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzMwMDA4NSBTYWx0ZWRfX3OGy0cXmdyuS nQUuv/p04OKmdRvy+hC5f7aItl9p6Vb16WNhxXUvoFHBHCiwBFIcqXjZiK54ZtWBQAgfUhhX3Tt jmtscwm3s5Xii0MZV+To1CAqbwPbelHgL7QUt76DUxzfePp5/f9gQ5DH8DLXUtvj1Q72u9f2bti gPwDCl22nYrLsXKr7+98phCfecqkyM1+v/Q1dOjva4hUPCSm9TthdC0vGkLnLwNpovAPTlv1P0c 6rW69PfJY/Vs2rLHvG4kxaSL43JOXvsHBMOgn6WuMfEFYZQvcm424E+NcjHG9kS8zcZRrQ8WJUu nkBMhemGDLKjVtt3YfvOk9siKB5vSBnqagxwkYRHbXpjZMxU6bodqq8tZGp56gKZb/x+IjjVDMR KVb9j1bxgJp94W1fSqYkt9J2iyCg78wfm+yIcC7gOI8qA3dkcw6i5QlWTbfHSx+ZQG2z/5F1 X-Authority-Analysis: v=2.4 cv=JKw7s9Kb c=1 sm=1 tr=0 ts=688a0895 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=hn1M32U-3FIS6ASJhmIA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 2PFdu6NQ5JnM6eHUAQuX-sFCepIzhv5V X-Proofpoint-GUID: 2PFdu6NQ5JnM6eHUAQuX-sFCepIzhv5V X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-30_04,2025-07-30_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 priorityscore=1501 spamscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 clxscore=1015 mlxlogscore=999 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507300085 On 7/1/25 2:24 PM, Luo Jie wrote: > > > On 6/28/2025 12:21 AM, Konrad Dybcio wrote: >> On 6/26/25 4:31 PM, Luo Jie wrote: >>> The PPE (Packet Process Engine) hardware block is available on Qualcomm >>> IPQ SoC that support PPE architecture, such as IPQ9574. >>> >>> The PPE in IPQ9574 includes six integrated ethernet MAC for 6 PPE ports, >>> buffer management, queue management and scheduler functions. The MACs >>> can connect with the external PHY or switch devices using the UNIPHY PCS >>> block available in the SoC. >>> >>> The PPE also includes various packet processing offload capabilities >>> such as L3 routing and L2 bridging, VLAN and tunnel processing offload. >>> It also includes Ethernet DMA function for transferring packets between >>> ARM cores and PPE ethernet ports. >>> >>> This patch adds the base source files and Makefiles for the PPE driver >>> such as platform driver registration, clock initialization, and PPE >>> reset routines. >>> >>> Signed-off-by: Luo Jie >>> --- >> >> [...] >> >>> +static int ppe_clock_init_and_reset(struct ppe_device *ppe_dev) >>> +{ >>> +    unsigned long ppe_rate = ppe_dev->clk_rate; >>> +    struct device *dev = ppe_dev->dev; >>> +    struct reset_control *rstc; >>> +    struct clk_bulk_data *clks; >>> +    struct clk *clk; >>> +    int ret, i; >>> + >>> +    for (i = 0; i < ppe_dev->num_icc_paths; i++) { >>> +        ppe_dev->icc_paths[i].name = ppe_icc_data[i].name; >>> +        ppe_dev->icc_paths[i].avg_bw = ppe_icc_data[i].avg_bw ? : >>> +                           Bps_to_icc(ppe_rate); >>> +        ppe_dev->icc_paths[i].peak_bw = ppe_icc_data[i].peak_bw ? : >>> +                        Bps_to_icc(ppe_rate); >>> +    } >> >> Can you not just set ppe_dev->icc_paths to ppe_icc_data? >> >> Konrad > > The `avg_bw` and `peak_bw` for two of the PPE ICC clocks ('ppe' and > 'ppe_cfg') vary across different SoCs and they need to be read from > platform data. They are not pre-defined in `ppe_icc_data` array. > Therefore, we use this format to assign `icc_paths`, allowing us to > accommodate cases where `avg_bw` and `peak_bw` are not predefined. > Hope this is fine. Thanks. You're currently hardcoding the clock rate, which one of the comments suggests is where the bw values come from. Is there a formula that we could calculate the necessary bandwidth based on? We could then clk_get_rate() and do it dynamically Konrad