From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D33ED3546E0 for ; Thu, 21 May 2026 15:23:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779377026; cv=none; b=LYdXluDQqLx2PrHTfpu59NoCdTmKdHE8E/IU6tj0JktGAl2H8wh2z4ZJsDIPy9208Ux/wkpINgq5WCh1Sw/qVMUjI2ef0sBztbhoVG3hwcncUVRbubTlA1T5/y0vNfhkDC1MTHz5dwf/VVs0+vLanxeF1Y3a4NZrTnjKpoe8ACA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779377026; c=relaxed/simple; bh=4iVhgQXvMAIvYMMJCNMV58/gqPl4iGCwT5C4qqVbT4U=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=Facc8G+1L0jKKBtEYQ3nNjKyS20o95N1wn1IdGBVtN7fTTDnOTYw0n1c6/+f+/Ddj+1e/cjeu7i3srhM4qim1BFmpXkcvNAE4fh8oIwIZxGrlgGV6/9JajfjTiR6Kyv5T7i1jp01+8adNvaSCVm05cwKKkyQnC287krzXkvvIPk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IC6aMezS; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IC6aMezS" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E9A631F00A3B; Thu, 21 May 2026 15:23:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779377024; bh=YLt8pB3gc5W3OLRvOCJT6J3/tZ5peumLWELk4xY5RWA=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=IC6aMezS8r69RfnNp9fQIEKuPeldqRhVXZoiF6Nna5mTyLpxpoinnMw31COojWkjh /I1VDNUMmZicCqDPFNbX19Wkx0oDRLBLY8OzYPmP1PEgo+Ui4OLLgupjeGLVDawU5H 84CmSKCW9piKnk4d82kPLONQh8SxwPpUXyLBPPYwykR/ofEqF6CyJ5toxgYM47bzYU boRIq7+YeGzBvfnAZ00npSHi3cAAimTGCyurnv+XhBKtZD4vf9tpMSh7jwI5uzUArn 8RyTxdogxQE3rglb8KWo5NsHaqBIsbNNDBIuvB3/WIELeaHIcwHlMLNejSmspYbQHn eUaHqgNnYuusQ== Message-ID: <4ea63bf6-d9ec-483d-a9c4-9715ec5547bc@kernel.org> Date: Thu, 21 May 2026 17:23:41 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/1] arm64: defconfig: Enable CIX Sky1 pinctrl, PCIe host, and Cadence GPIO To: Peter Chen , arnd@arndb.de Cc: krzysztof.kozlowski@oss.qualcomm.com, geert+renesas@glider.be, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, cix-kernel-upstream@cixtech.com, Yunseong Kim References: <20260327114628.3800886-1-peter.chen@cixtech.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 27/03/2026 12:46, Peter Chen wrote: > Enable the CIX Sky1 pinctrl driver (PINCTRL_SKY1), CIX Sky1 PCIe host > controller (PCI_SKY1_HOST), and Cadence GPIO controller (GPIO_CADENCE) > for the Radxa Orion O6 board which uses the CIX Sky1 SoC. > > The pinctrl driver is a dependency for other on-SoC peripherals. The > Cadence-based PCIe host controller enables use of PCIe peripherals on > the board. The Cadence GPIO controller provides GPIO support for the > SoC. > > Cc: Yunseong Kim > Signed-off-by: Peter Chen > --- > Changes for v3: > - Use specific driver names (CIX Sky1 pinctrl, CIX Sky1 PCIe host > controller, Cadence GPIO) in subject and commit message instead of > generic terms. > - Remove external Debian bug reference; explain rationale directly. > - Remove NVMe mention since only PCIe host controller is enabled. > > Changes for v2: > - Delete CIX HDA configurations due to it is not used at current > Orion O6 board device tree. > > arch/arm64/configs/defconfig | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > index b67d5b1fc45b..f9be52484008 100644 > --- a/arch/arm64/configs/defconfig > +++ b/arch/arm64/configs/defconfig > @@ -241,6 +241,7 @@ CONFIG_PCIE_XILINX_DMA_PL=y > CONFIG_PCIE_XILINX_NWL=y > CONFIG_PCIE_XILINX_CPM=y > CONFIG_PCI_J721E_HOST=m > +CONFIG_PCI_SKY1_HOST=m This is not correctly placed and caused issues later - conflicts with my cleanup patch. Please fix it up before you send the patch to soc@. Best regards, Krzysztof