From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x224p9BsWmRlKeQ4S9YFTy33A0QbMVCmN0Y2T7/oWcEpSYvkM2KAbnc1kngqETK8Q/qupB38N ARC-Seal: i=1; a=rsa-sha256; t=1516537381; cv=none; d=google.com; s=arc-20160816; b=ZZeMRfAI9KHCoLQ93w9PDMUVKajw82OW0leL0Tlo09NKuPISApFopT+EVDY3LsibHi 2FvaN3HpA73CXutVQr3kLWyF2QZFq9mcsJ2KO6y4naIvNq+ZwV44eJv/QXnAgLIaB6yL qoW4DC3NaWg9gtypETdZZzu6RkATdFSkqruhm3h0FF3v4rpgzsqlnfC0CZhZ2/4eV4bP PyumxnDbsAvSykjHGexvHe3lIMM96EIma4yrK6bwByY6ePnqirgydu/2+RMCVDJjuazm 5z3BilnjGV5LDKqM0WUWGPOI0x3kQwz3WxLyTWOfQ0FvccIJn6d57Q1Ixacv6z6Cjh3I d/PQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=importance:content-transfer-encoding:mime-version:user-agent:cc:to :from:subject:date:references:in-reply-to:message-id:dkim-signature :arc-authentication-results; bh=4gEp5nxYGwfuIQVoIDfLGE6L7NdtVFvQ3Hx217eBDeQ=; b=GxA+Ds6wY+S5bYM/6Wg1Xw8TuGNz5J4l9NT8tW8a3HscLSXvej47Qu+KhSXhhgbUaB G0dnpWCNE2btPQj2IzYptX53YvNzwgd+YVmNEs3CVEdsvbwItgb9+9ZzUanTpyWYTWiP Sg42d9wpPyklcYGGhBL2Y6TCvbNjeotmWcwVC9OMnQYnJ51Ha8L37Zjx00H2jfrnJUJG GllS0ob6SAhvobY4IE9UfpmEhLbsUY0jpPeE4wvGco0wjURIljZ6HOadoA55SZawHlAA jCBuYjs5Y/+PveA76/ExU2OGxkOtd8L5cuzpKNdiyZnpXJrhpVZrqkZ4IthHt9HKdHVR UPjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@infradead.org header.s=twosheds.20170209 header.b=RLVUDQKW; spf=pass (google.com: best guess record for domain of batv+c3727a9e9cf4ad240057+5264+infradead.org+dwmw2@twosheds.srs.infradead.org designates 2001:8b0:10b:1:21d:7dff:fe04:dbe2 as permitted sender) smtp.mailfrom=BATV+c3727a9e9cf4ad240057+5264+infradead.org+dwmw2@twosheds.srs.infradead.org Authentication-Results: mx.google.com; dkim=pass header.i=@infradead.org header.s=twosheds.20170209 header.b=RLVUDQKW; spf=pass (google.com: best guess record for domain of batv+c3727a9e9cf4ad240057+5264+infradead.org+dwmw2@twosheds.srs.infradead.org designates 2001:8b0:10b:1:21d:7dff:fe04:dbe2 as permitted sender) smtp.mailfrom=BATV+c3727a9e9cf4ad240057+5264+infradead.org+dwmw2@twosheds.srs.infradead.org Message-ID: <4eb681c76b549ddad43544f2b487106c.squirrel@twosheds.infradead.org> In-Reply-To: <20180121121638.jpwyk4npxjcgqzar@pd.tnic> References: <1516449813-7654-1-git-send-email-dwmw@amazon.co.uk> <1516449813-7654-3-git-send-email-dwmw@amazon.co.uk> <20180121121638.jpwyk4npxjcgqzar@pd.tnic> Date: Sun, 21 Jan 2018 12:22:47 -0000 Subject: Re: [PATCH 2/4] x86/cpufeatures: Add AMD feature bits for Prediction Command From: "David Woodhouse" To: "Borislav Petkov" Cc: "David Woodhouse" , "Tom Lendacky" , arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org User-Agent: SquirrelMail/1.4.22-21.fc27 MIME-Version: 1.0 Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: 8bit X-Priority: 3 (Normal) Importance: Normal X-SRS-Rewrite: SMTP reverse-path rewritten from by twosheds.infradead.org. See http://www.infradead.org/rpr.html X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590112908013365211?= X-GMAIL-MSGID: =?utf-8?q?1590204701869103213?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: > On Sat, Jan 20, 2018 at 12:03:31PM +0000, David Woodhouse wrote: >> AMD doesn't implement the Speculation Control MSR that Intel does, but >> the Prediction Control MSR does exist and is advertised by a separate >> CPUID bit. Add support for that. >> >> Signed-off-by: David Woodhouse >> --- >> arch/x86/include/asm/cpufeatures.h | 1 + >> arch/x86/kernel/cpu/scattered.c | 1 + >> 2 files changed, 2 insertions(+) >> >> diff --git a/arch/x86/include/asm/cpufeatures.h >> b/arch/x86/include/asm/cpufeatures.h >> index adebdaa..624d978 100644 >> --- a/arch/x86/include/asm/cpufeatures.h >> +++ b/arch/x86/include/asm/cpufeatures.h >> @@ -207,6 +207,7 @@ >> #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* AMD Retpoline >> mitigation for Spectre variant 2 */ >> #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory >> Number */ >> >> +#define X86_FEATURE_AMD_PRED_CMD ( 7*32+17) /* Prediction Command MSR >> (AMD) */ > > Right, so this bit I've seen being called differently. Tom, can you > clarify pls? Yeah, that's fat-fingered in a cut/paste in refactoring. Fixed in what I posted this morning. I would like to see public docs with it though... Tom? -- dwmw2