From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Long Zhao <longzhao@ambarella.com>
Cc: Arnd Bergmann <arnd@arndb.de>,
Krzysztof Kozlowski <krzk@kernel.org>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Jerome Brunet <jbrunet@baylibre.com>,
Linus Walleij <linusw@kernel.org>,
Bartosz Golaszewski <brgl@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jirislaby@kernel.org>,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Long Zhao <zl020895@163.com>,
Lee Jones <lee@kernel.org>,
mfd@lists.linux.dev, devicetree@vger.kernel.org,
linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,
linux-serial <linux-serial@vger.kernel.org>,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v7 13/15] serial: 8250_dw: add Ambarella CV75 quirks
Date: Tue, 15 Sep 2026 14:47:07 +0300 (EEST) [thread overview]
Message-ID: <4eca948b-ebf7-ee86-78e8-af886f19ed0c@linux.intel.com> (raw)
In-Reply-To: <20260915-cv75-v5-v7-13-3297d3fbc9c0@ambarella.com>
[-- Attachment #1: Type: text/plain, Size: 3543 bytes --]
On Tue, 15 Sep 2026, Long Zhao via B4 Relay wrote:
> From: Long Zhao <longzhao@ambarella.com>
>
> The Ambarella CV75 UART is Ambarella IP, not a Synopsys DesignWare
> licensed block. At the register level it is close enough to DW APB UART
> that a full custom UART driver is unnecessary: reuse 8250_dw with a
> small platform quirk.
>
> Quirks:
> - keep IER ETOI (bit 5) set for RX timeout behaviour
> - skip set_rate; baud clock is managed outside the UART block
>
> Reviewed-by: Linus Walleij <linusw@kernel.org>
> Signed-off-by: Long Zhao <longzhao@ambarella.com>
> ---
> drivers/tty/serial/8250/8250_dw.c | 32 ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> index 5fba913f3301..19431c476c55 100644
> --- a/drivers/tty/serial/8250/8250_dw.c
> +++ b/drivers/tty/serial/8250/8250_dw.c
> @@ -43,6 +43,9 @@
> #define RZN1_UART_xDMACR_8_WORD_BURST (2 << 1)
> #define RZN1_UART_xDMACR_BLK_SZ(x) ((x) << 3)
>
> +/* Ambarella IER: receive timeout interrupt enable */
> +#define AMBARELLA_UART_IER_ETOI BIT(5)
> +
> /* Quirks */
> #define DW_UART_QUIRK_OCTEON BIT(0)
> #define DW_UART_QUIRK_ARMADA_38X BIT(1)
> @@ -60,6 +63,7 @@
>
> struct dw8250_platform_data {
> u8 usr_reg;
> + u8 ier_mask;
> u32 cpr_value;
> unsigned int quirks;
> };
> @@ -572,6 +576,25 @@ static void dw8250_prepare_rx_dma(struct uart_8250_port *p)
> dw8250_writel_ext(up, RZN1_UART_RDMACR, val);
> }
>
> +static int dw8250_ier_mask_startup(struct uart_port *p)
> +{
> + struct dw8250_data *d = to_dw8250_data(p->private_data);
> + struct uart_8250_port *up = up_to_u8250p(p);
> + int ret;
> +
> + ret = serial8250_do_startup(p);
> + if (ret)
> + return ret;
> +
> + /*
> + * Ambarella keeps variant IER bits (e.g. ETOI) set for correct RX
> + * timeout behaviour.
> + */
> + up->ier |= d->pdata->ier_mask;
> +
> + return 0;
> +}
> +
> static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
> {
> unsigned int quirks = data->pdata->quirks;
> @@ -606,6 +629,8 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
> p->serial_in = dw8250_serial_in32;
> data->uart_16550_compatible = true;
> }
> + if (data->pdata->ier_mask)
> + p->startup = dw8250_ier_mask_startup;
> }
>
> static void dw8250_reset_control_assert(void *data)
> @@ -879,6 +904,12 @@ static const struct dw8250_platform_data dw8250_intc10ee = {
> .quirks = DW_UART_QUIRK_IER_KICK,
> };
>
> +static const struct dw8250_platform_data dw8250_ambarella_cv75_data = {
> + .usr_reg = DW_UART_USR,
> + .ier_mask = AMBARELLA_UART_IER_ETOI,
> + .quirks = DW_UART_QUIRK_SKIP_SET_RATE,
> +};
> +
> static const struct dw8250_platform_data dw8250_ultrarisc_dp1000_data = {
> .usr_reg = DW_UART_USR,
> .cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) |
> @@ -889,6 +920,7 @@ static const struct dw8250_platform_data dw8250_ultrarisc_dp1000_data = {
> };
>
> static const struct of_device_id dw8250_of_match[] = {
> + { .compatible = "ambarella,cv75-uart", .data = &dw8250_ambarella_cv75_data },
> { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
> { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
> { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
--
i.
next prev parent reply other threads:[~2026-09-15 11:47 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-15 11:15 [PATCH v7 00/15] Ambarella CV75 SoC minimal bring-up Long Zhao via B4 Relay
2026-09-15 11:15 ` [PATCH v7 01/15] dt-bindings: arm: add Ambarella CV75 platforms Long Zhao via B4 Relay
2026-09-15 11:15 ` [PATCH v7 02/15] dt-bindings: mfd: syscon: add Ambarella CV75 secure scratchpad Long Zhao via B4 Relay
2026-09-15 11:15 ` [PATCH v7 03/15] dt-bindings: clock: add Ambarella CV75 RCT Long Zhao via B4 Relay
2026-09-15 11:15 ` [PATCH v7 04/15] dt-bindings: pinctrl: add Ambarella CV75 pinctrl Long Zhao via B4 Relay
2026-09-15 11:15 ` [PATCH v7 05/15] dt-bindings: gpio: pl061: add Ambarella CV75 variant Long Zhao via B4 Relay
2026-09-15 11:15 ` [PATCH v7 06/15] dt-bindings: serial: snps-dw-apb-uart: add ambarella,cv75-uart Long Zhao via B4 Relay
2026-09-15 11:15 ` [PATCH v7 07/15] clk: ambarella: add CV75 RCT clock controller Long Zhao via B4 Relay
2026-09-15 13:24 ` Uwe Kleine-König
2026-09-15 13:27 ` Andy Shevchenko
2026-09-15 11:15 ` [PATCH v7 08/15] gpiolib: regmap: add write_data_after_dir quirk Long Zhao via B4 Relay
2026-09-15 15:07 ` Andy Shevchenko
2026-09-16 4:47 ` zl020895
2026-09-15 11:15 ` [PATCH v7 09/15] gpiolib: regmap: add gpio_regmap_get_chip() Long Zhao via B4 Relay
2026-09-15 15:30 ` Andy Shevchenko
2026-09-16 4:49 ` zl020895
2026-09-15 11:15 ` [PATCH v7 10/15] gpio: pl061: convert to gpio-regmap and a custom irqchip Long Zhao via B4 Relay
2026-09-16 10:21 ` Andy Shevchenko
2026-09-15 11:15 ` [PATCH v7 11/15] gpio: pl061: add Ambarella register-layout variant Long Zhao via B4 Relay
2026-09-16 10:51 ` Andy Shevchenko
2026-09-15 11:15 ` [PATCH v7 12/15] pinctrl: ambarella: add CV75 pin controller Long Zhao via B4 Relay
2026-09-16 10:49 ` Andy Shevchenko
2026-09-17 9:06 ` zl020895
2026-09-17 12:22 ` Andy Shevchenko
2026-09-17 12:55 ` zl020895
2026-09-15 11:15 ` [PATCH v7 13/15] serial: 8250_dw: add Ambarella CV75 quirks Long Zhao via B4 Relay
2026-09-15 11:47 ` Ilpo Järvinen [this message]
2026-09-15 13:21 ` Andy Shevchenko
2026-09-15 11:15 ` [PATCH v7 14/15] arm64: ambarella: add ARCH_AMBARELLA and CV75 EVK DT Long Zhao via B4 Relay
2026-09-15 11:15 ` [PATCH v7 15/15] MAINTAINERS: add ARM/AMBARELLA SoC support Long Zhao via B4 Relay
2026-09-16 9:14 ` [PATCH v7 00/15] Ambarella CV75 SoC minimal bring-up Bartosz Golaszewski
2026-09-16 9:42 ` Linus Walleij
2026-09-16 10:23 ` Andy Shevchenko
2026-09-16 11:01 ` zl020895
2026-09-16 15:20 ` Andy Shevchenko
2026-09-17 9:05 ` zl020895
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