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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-667af38d891sm1582078a12.9.2026.03.18.04.29.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Mar 2026 04:29:39 -0700 (PDT) Message-ID: <4ed72391-fcd2-4ad7-94da-45fe13012953@oss.qualcomm.com> Date: Wed, 18 Mar 2026 12:29:37 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/2] arm64: dts: qcom: sm8250-asus-obiwan: Add ASUS ROG Phone 3 To: Alexander Koskovich , Dmitry Baryshkov Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260310-sm8250-asus-obiwan-v3-0-9ed8f0e71e19@pm.me> <20260310-sm8250-asus-obiwan-v3-2-9ed8f0e71e19@pm.me> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE4MDA5NyBTYWx0ZWRfX3ApicNpyYm9v yQ0X2A4H+1p4MqnEEJML9OpIXsPMKVlhAieEnBfM9rG/9Dw/YKxAVY02TytP3ucxaS0QLAEgVFf C4rbtsNIqOu7dtOTjgBDvtkMb6430IQkUBKiEj/Fau77rqRHvMXwWxCheQGCtvXgxL+KB0fHc08 DngBTLcLTVGLX1DOj8NulZ9SmZpqTutVdyZ3fifj+vsdNv0nWMnLPBwD05vqz3TeaVTdbisxNH5 s8u9FC5xYyQd5B7KbSieconlnwYLX4b7DgSbc0g43G1Br0TFKvKzspbcM+LAyY1fD+CvYdJ/8L5 bYC6kCk+rf79FMkKJrevobsQK63rFBL1z6U19HLq60vr6hPkFB8e4JGpE3dPplH0yHYTpamyI23 fBhMf4+2qXaTYo3kDwHZmZCN8WrnHP+8/DeFV1Z6SZf7GvFUVZfJAIWiRm9y9XgQLpxmzXOBsXX gqYNBRFy7WE7YHvgjNQ== X-Authority-Analysis: v=2.4 cv=P8I3RyAu c=1 sm=1 tr=0 ts=69ba8ca5 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=VwQbUJbxAAAA:8 a=cm27Pg_UAAAA:8 a=EUspDBNiAAAA:8 a=SwhEMycmah-h3sa3uUYA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-ORIG-GUID: 1Rq7TQGPtZZcLD8eLrOfIjtOhpoOX6hL X-Proofpoint-GUID: 1Rq7TQGPtZZcLD8eLrOfIjtOhpoOX6hL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-18_01,2026-03-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 malwarescore=0 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603180097 On 3/18/26 12:14 PM, Alexander Koskovich wrote: > On Wednesday, March 18th, 2026 at 6:28 AM, Konrad Dybcio wrote: > >>> + /* >>> + * There are also ER & EVB boards, but those have meaningful hardware >>> + * differences that make them not compatible with this devicetree. >>> + */ >>> + qcom,board-id = <31 0>, /* ER2 */ >>> + <40 0>, /* PR */ >>> + <41 0>, /* PR2 */ >>> + <50 0>; /* MP */ >> >> I would guesstimate MP is Mass Production and everything before that is >> engineering samples.. perhaps that doesn't hurt - maybe some curious Asus >> engineer swings by one day! > > Actually the unit I have is 'PR', it's one I got from ASUS when they were still > sending out phones to developers. I guess the units they shipped out were preprod. Oh, nice! Maybe 'public relations'.. >>> + source-pdos = >> + PDO_FIXED_DUAL_ROLE | >>> + PDO_FIXED_USB_COMM | >>> + PDO_FIXED_DATA_SWAP)>; >>> + >>> + sink-pdos = >> + PDO_FIXED_DUAL_ROLE | >>> + PDO_FIXED_USB_COMM | >>> + PDO_FIXED_DATA_SWAP) >>> + PDO_FIXED(9000, 3000, 0) >>> + PDO_FIXED(12000, 2250, 0)>; >> >> Both ports have the same PDOs - will this kaboom if you plug in two chargers? > > Good catch, from what I can see there is zero hardware isolation. Downstream > prevents dual sink by only allowing one port to negotiate sink at a time (seems > to always prefer usb_1 if both are plugged in, guessing because its used for > the dock), but there is no upstream mechanism to handle this as far as I know > (not sure if this could even be done cleanly as it'd require cooperation > between pm8150b_typec and rt1715). Could you please remind me how the two were connected? Maybe we can work something out. Sounds like it would make sense for the two to have *some* sort of relationship described > > Will just drop the sink PDOs from usb_2 and have it be only source to avoid > this issue. SG as a workaround >>> +&usb_2 { >>> + pinctrl-0 = <&rt1715_mux_en>, <&usb2_mux_en>; >>> + pinctrl-names = "default"; >>> + >>> + /* >>> + * Disable USB3 clock requirement as the bottom port only supports USB2. >>> + * The USB3 lanes are routed through the pogo connector on this board for >>> + * use with accessories, so will need to revisit this when we start to add >>> + * support for those. >>> + */ >>> + qcom,select-utmi-as-pipe-clk; >> >> So, is that right? >> >> ┌───────┐ >> │ POGO │ >> └──┬──┬─┘ >> superspeed │ │ >> ┌─────────────────────────────┘ │ >> │ │ >> ┌──────┼─┐ highspeed │ >> │ DWC3_2 ┼─────────────────────┐ ┌────┴──┐ >> └────────┘ └───┤ MUX ┼───────PM8150_GPIO9 >> ┌─────────┐ └──┬────┘ >> │ GPIO170 │ │ >> └─────────┘ │ >> │ │ >> ┌────────┐ RXTX ┌───┴──┐ ┌───┴──┐ >> │ UART ┼────────│ MUX ┼────────┤USB-C2│ >> └────────┘ └──┬───┘ └──────┘ >> │ >> ▼ >> GND > > I misspoke in v3, UART is not controlled via a mux it's just a gate. Was > looking at the board previously and it seemed it either went to test points on > the board, or USB. But the enable GPIO controls both. Have it renamed in v4 > staging atm. > > But yeah that is accurate otherwise wrt the USB 2 mux. Okay.. I don't know whether we have infra to handle it today (+Dmitry?) but generally we'd need something like usb-mux { select-gpios = <&tlmm foo bar>; // sense it via some notification? ports { // conn to usb_2_hs // conn to type-c // conn to pogo pin connector }; }; rt1715 { connector { // mux conn } } pogo-pins-connector { // mux conn } there was a similar attempt (I bumped it up.. maybe it'll be merged soon) at describing a pogo pin connector, so part of that may come in useful: https://lore.kernel.org/all/20250225223038.879614-2-swboyd@chromium.org/ but in any case, that's a song of the future.. Konrad