From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 506B7C433EF for ; Fri, 8 Jul 2022 08:13:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237728AbiGHINl (ORCPT ); Fri, 8 Jul 2022 04:13:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237722AbiGHINi (ORCPT ); Fri, 8 Jul 2022 04:13:38 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25712DF00; Fri, 8 Jul 2022 01:13:33 -0700 (PDT) Received: from [192.168.1.100] (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 9740266019D1; Fri, 8 Jul 2022 09:13:31 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1657268012; bh=HhAChS+K51bNxk2DP8DUaQ+Ar93nqS3yFt69vVEpOAs=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=gddanjJlgH7sblqg1l5mhtUMLcnLujTx9cXAHJQt/10tGHweIpsrFhN6Ejrlh/hG9 qtDuSgSt3Phf/lLKcMlXPPQJt58QfRq4y82tAgGWwDEF8KxT4fooZ4OkmZcE+jvKsn /Awe+K6tRYxnKH09anJIqduc0qmX/r3ykRHfIXWk/5JBZFyoFdSRO5UCr4z0dRkSC/ J4tVZuS6m0FY7ILMjHZqvqA1XBFOd/MqGag1zyTGT1zg1SH0In1A9wZXhdT9G0WihD ATyL7xODW1vGgZastds30am/aqvaUKXmndDvNNAfgbsBvUpYwdNs+vu8ZcQDfGwL52 J5mMHHw2WiKqg== Message-ID: <4ee027c3-fbfb-52dd-fa38-74dcff526bf5@collabora.com> Date: Fri, 8 Jul 2022 10:13:29 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [RESEND v4 2/2] i2c: mediatek: Add i2c compatible for Mediatek MT8188 Content-Language: en-US To: kewei.xu@mediatek.com, wsa@the-dreams.de Cc: matthias.bgg@gmail.com, robh+dt@kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, leilk.liu@mediatek.com, qii.wang@mediatek.com, liguo.zhang@mediatek.com, caiyu.chen@mediatek.com, housong.zhang@mediatek.com, yuhan.wei@mediatek.com, david-yh.chiu@mediatek.com, liju-clr.chen@mediatek.com References: <20220708034758.22747-1-kewei.xu@mediatek.com> <20220708034758.22747-2-kewei.xu@mediatek.com> From: AngeloGioacchino Del Regno In-Reply-To: <20220708034758.22747-2-kewei.xu@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Il 08/07/22 05:47, kewei.xu@mediatek.com ha scritto: > From: Kewei Xu > > Add i2c compatible for MT8188. Compare to MT8192 i2c controller, > The MT8188 i2c OFFSET_SLAVE_ADDR register changed from 0x04 to 0x94. > > Signed-off-by: Kewei Xu > --- > v4: no changes > V3: no changes > V2: added mt_i2c_regs_v3[] to replace slave_addr_version. > --- > drivers/i2c/busses/i2c-mt65xx.c | 43 +++++++++++++++++++++++++++++++++ > 1 file changed, 43 insertions(+) > > diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c > index 8e6985354fd5..70aff42adf5d 100644 > --- a/drivers/i2c/busses/i2c-mt65xx.c > +++ b/drivers/i2c/busses/i2c-mt65xx.c > @@ -229,6 +229,35 @@ static const u16 mt_i2c_regs_v2[] = { > [OFFSET_DCM_EN] = 0xf88, > }; > > +static const u16 mt_i2c_regs_v3[] = { > + [OFFSET_DATA_PORT] = 0x0, > + [OFFSET_SLAVE_ADDR] = 0x94, Please keep this list ordered by register offset. > + [OFFSET_INTR_MASK] = 0x8, > + [OFFSET_INTR_STAT] = 0xc, > + [OFFSET_CONTROL] = 0x10, > + [OFFSET_TRANSFER_LEN] = 0x14, > + [OFFSET_TRANSAC_LEN] = 0x18, > + [OFFSET_DELAY_LEN] = 0x1c, > + [OFFSET_TIMING] = 0x20, > + [OFFSET_START] = 0x24, > + [OFFSET_EXT_CONF] = 0x28, > + [OFFSET_LTIMING] = 0x2c, > + [OFFSET_HS] = 0x30, > + [OFFSET_IO_CONFIG] = 0x34, > + [OFFSET_FIFO_ADDR_CLR] = 0x38, > + [OFFSET_SDA_TIMING] = 0x3c, > + [OFFSET_TRANSFER_LEN_AUX] = 0x44, > + [OFFSET_CLOCK_DIV] = 0x48, > + [OFFSET_SOFTRESET] = 0x50, > + [OFFSET_MULTI_DMA] = 0x8c, > + [OFFSET_SCL_MIS_COMP_POINT] = 0x90, [OFFSET_SLAVE_ADDR] = 0x94 goes here, after which: Reviewed-by: AngeloGioacchino Del Regno