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Mon, 15 Sep 2025 03:55:33 -0500 Received: from DFLE202.ent.ti.com (10.64.6.60) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 15 Sep 2025 03:55:33 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE202.ent.ti.com (10.64.6.60) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Mon, 15 Sep 2025 03:55:33 -0500 Received: from [172.24.233.20] (a0512632.dhcp.ti.com [172.24.233.20]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 58F8tSDU3764317; Mon, 15 Sep 2025 03:55:29 -0500 Message-ID: <4f0a00d9-4edc-4114-aca6-70d6bb654767@ti.com> Date: Mon, 15 Sep 2025 14:25:27 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 3/3] drm/tidss: oldi: Add atomic_check hook for oldi bridge To: Maxime Ripard CC: , , , , , , , , , , , , , References: <20250911110715.2873596-1-s-jain1@ti.com> <20250911110715.2873596-4-s-jain1@ti.com> <20250915-benevolent-military-penguin-d64871@penduick> Content-Language: en-US From: Swamil Jain In-Reply-To: <20250915-benevolent-military-penguin-d64871@penduick> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Hi, On 9/15/25 13:27, Maxime Ripard wrote: > On Thu, Sep 11, 2025 at 04:37:15PM +0530, Swamil Jain wrote: >> From: Jayesh Choudhary >> >> Since OLDI consumes DSS VP clock directly as serial clock, mode_valid() >> check cannot be performed in tidss driver which should be checked >> in OLDI driver. >> >> Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support") >> Tested-by: Michael Walle >> Reviewed-by: Devarsh Thakkar >> Signed-off-by: Jayesh Choudhary >> Signed-off-by: Swamil Jain >> --- >> drivers/gpu/drm/tidss/tidss_oldi.c | 21 +++++++++++++++++++++ >> 1 file changed, 21 insertions(+) >> >> diff --git a/drivers/gpu/drm/tidss/tidss_oldi.c b/drivers/gpu/drm/tidss/tidss_oldi.c >> index 7ecbb2c3d0a2..ada691839ef3 100644 >> --- a/drivers/gpu/drm/tidss/tidss_oldi.c >> +++ b/drivers/gpu/drm/tidss/tidss_oldi.c >> @@ -309,6 +309,26 @@ static u32 *tidss_oldi_atomic_get_input_bus_fmts(struct drm_bridge *bridge, >> return input_fmts; >> } >> >> +static int tidss_oldi_atomic_check(struct drm_bridge *bridge, >> + struct drm_bridge_state *bridge_state, >> + struct drm_crtc_state *crtc_state, >> + struct drm_connector_state *conn_state) >> +{ >> + struct tidss_oldi *oldi = drm_bridge_to_tidss_oldi(bridge); >> + struct drm_display_mode *adjusted_mode; >> + unsigned long round_clock; >> + >> + adjusted_mode = &crtc_state->adjusted_mode; >> + round_clock = clk_round_rate(oldi->serial, adjusted_mode->clock * 7 * 1000); >> + /* >> + * To keep the check consistent with dispc_vp_set_clk_rate(), >> + * we use the same 5% check here. >> + */ >> + if (dispc_pclk_diff(adjusted_mode->clock * 7 * 1000, round_clock) > 5) >> + return -EINVAL; >> + return 0; >> +} >> + > > If you're introducing that check to tidss, please use .5% like everyone > else. I understand that you don't want to change tilcdc to avoid any > regression, but that's not the case here > This is just to make the tolerance check consistent for mode validation and setting clock rate. This patch isn't introducing anything new, we are following this as dispc_vp_set_clk_rate() and tidss_oldi_set_serial_clk() are already checking for 5% tolerance while setting clock. To remove/modify, this needs extensive testing with other K3 and K2G SoCs and can be handled as a separate patch. Regards, Swamil > Maxime