From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99EBB1428FE; Mon, 29 Jul 2024 10:18:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722248339; cv=none; b=PZWWv/X4X7wo6hd80Neymg2q1s7XdmdNMbEGduLDm9z7bhtDzu84JYdkuHLGIk9schFqqShcGZbVIJUjll5lHeqlgGHdTcQJm0D+r3kut8umcq5lgG3xfq/T5Jm095sC0U7V79l6VeK+b/LTCbCPFdiOAcmkD02KCOWcFB6yFgA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722248339; c=relaxed/simple; bh=A6pRdJOG1auLDR9ZXiKkrNKgnD/M/3p7mp0/E7Sbs1U=; h=Message-ID:Date:MIME-Version:Subject:To:CC:References:From: In-Reply-To:Content-Type; b=FdtRpVA29L1zp0AUC+Az8fuoxqKFME90XG1AOWkoSCRuW2LvcFXWBShF+vnd0wC0Wq9OamrzS2YgNomR5FlXmoD4TQmFC577ay991Zb6zVY0tU6mb6ShDg4mpNo+7Wg7Wk4K8v4DGFDbgNihWS6+KSuVxON2omEO9YM4bGOXNfA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=P/De3VFE; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="P/De3VFE" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 46SNQNFT026407; Mon, 29 Jul 2024 10:18:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= e94lcA7O09IiVanGDyLpRv1btlDhG6LYVdZVJ8WsfQo=; b=P/De3VFEaqcyRGTx p/tXWkUP6J66cVL4Uwb81/b5U9sZZIm4TM3gjTYNSTWcAyO2MsPGDOwvdBK+pffl wTCWZMDSSf9rZg1d4gxEDRFRnRmim4rItVycscynTqcrHIJz2WMwxqrLfj74V8yb Lm4YfolokxM1EvKUxebBFtNpUFxxJX9fefvfoSg4FzqY1b2BTxJkZia6+OIo7RlN 3DP4pbGcB7Kf0aYwtddm2TCA+ElEg9EE1Mxhvg2vjo2cG/U2YUvuLyLd3TuB9OPh dv70Y4Rm/rVz0Ex6Al8F3cFE65ybZgGfwUFATDzCz+mUUzRg3XeLxlligTn+5bzk wQXYMA== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 40mpkev1h0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 29 Jul 2024 10:18:43 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46TAIgKG002943 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 29 Jul 2024 10:18:42 GMT Received: from [10.239.132.204] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 29 Jul 2024 03:18:38 -0700 Message-ID: <4f144be9-96d9-4fa7-9a1d-53a68a329b98@quicinc.com> Date: Mon, 29 Jul 2024 18:18:35 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] dt-bindings: interrupt-controller: qcom,pdc: document pdc on QCS9100 To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson CC: , , , References: <20240709-document_qcs9100_pdc_compatible-v2-1-83619dcd2658@quicinc.com> From: Tengfei Fan In-Reply-To: <20240709-document_qcs9100_pdc_compatible-v2-1-83619dcd2658@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: RTzDRmcYTRcWFGdDnHm8SRZzMvCuUqZr X-Proofpoint-GUID: RTzDRmcYTRcWFGdDnHm8SRZzMvCuUqZr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-29_08,2024-07-26_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 malwarescore=0 lowpriorityscore=0 spamscore=0 phishscore=0 adultscore=0 mlxscore=0 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407290069 On 7/9/2024 9:56 PM, Tengfei Fan wrote: > The QCS9100 SoC includes a PDC, document it. > QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p > platform use non-SCMI resource. In the future, the SA8775p platform will > move to use SCMI resources and it will have new sa8775p-related device > tree. Consequently, introduce "qcom,qcs9100-pdc" to describe non-SCMI > based pdc. > > Signed-off-by: Tengfei Fan > --- > Introduce support for the QCS9100 SoC device tree (DTSI) and the > QCS9100 RIDE board DTS. The QCS9100 is a variant of the SA8775p. > While the QCS9100 platform is still in the early design stage, the > QCS9100 RIDE board is identical to the SA8775p RIDE board, except it > mounts the QCS9100 SoC instead of the SA8775p SoC. > > The QCS9100 SoC DTSI is directly renamed from the SA8775p SoC DTSI, and > all the compatible strings will be updated from "SA8775p" to "QCS9100". > The QCS9100 device tree patches will be pushed after all the device tree > bindings and device driver patches are reviewed. > > The final dtsi will like: > https://lore.kernel.org/linux-arm-msm/20240703025850.2172008-3-quic_tengfan@quicinc.com/ > > The detailed cover letter reference: > https://lore.kernel.org/linux-arm-msm/20240703025850.2172008-1-quic_tengfan@quicinc.com/ > --- > Changes in v2: > - Split huge patch series into different patch series according to > subsytems > - Update patch commit message > > prevous disscussion here: > [1] v1: https://lore.kernel.org/linux-arm-msm/20240703025850.2172008-1-quic_tengfan@quicinc.com/ > --- > Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml > index 985fa10abb99..41fbfce838fa 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml > @@ -26,6 +26,7 @@ properties: > compatible: > items: > - enum: > + - qcom,qcs9100-pdc > - qcom,qdu1000-pdc > - qcom,sa8775p-pdc > - qcom,sc7180-pdc > > --- > base-commit: 0b58e108042b0ed28a71cd7edf5175999955b233 > change-id: 20240709-document_qcs9100_pdc_compatible-65e4066b1728 > > Best regards, After considering the feedback provided on the subject, We have decided to keep current SA8775p compatible and ABI compatibility in drivers. Let's close this session and ignore the current patche here. Thank you for your input. -- Thx and BRs, Tengfei Fan