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Bae" , linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com References: <20260630191350.3837-1-chang.seok.bae@intel.com> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; keydata= xsFNBE6HMP0BEADIMA3XYkQfF3dwHlj58Yjsc4E5y5G67cfbt8dvaUq2fx1lR0K9h1bOI6fC oAiUXvGAOxPDsB/P6UEOISPpLl5IuYsSwAeZGkdQ5g6m1xq7AlDJQZddhr/1DC/nMVa/2BoY 2UnKuZuSBu7lgOE193+7Uks3416N2hTkyKUSNkduyoZ9F5twiBhxPJwPtn/wnch6n5RsoXsb ygOEDxLEsSk/7eyFycjE+btUtAWZtx+HseyaGfqkZK0Z9bT1lsaHecmB203xShwCPT49Blxz VOab8668QpaEOdLGhtvrVYVK7x4skyT3nGWcgDCl5/Vp3TWA4K+IofwvXzX2ON/Mj7aQwf5W iC+3nWC7q0uxKwwsddJ0Nu+dpA/UORQWa1NiAftEoSpk5+nUUi0WE+5DRm0H+TXKBWMGNCFn c6+EKg5zQaa8KqymHcOrSXNPmzJuXvDQ8uj2J8XuzCZfK4uy1+YdIr0yyEMI7mdh4KX50LO1 pmowEqDh7dLShTOif/7UtQYrzYq9cPnjU2ZW4qd5Qz2joSGTG9eCXLz5PRe5SqHxv6ljk8mb ApNuY7bOXO/A7T2j5RwXIlcmssqIjBcxsRRoIbpCwWWGjkYjzYCjgsNFL6rt4OL11OUF37wL QcTl7fbCGv53KfKPdYD5hcbguLKi/aCccJK18ZwNjFhqr4MliQARAQABzUVEYXZpZCBDaHJp c3RvcGhlciBIYW5zZW4gKEludGVsIFdvcmsgQWRkcmVzcykgPGRhdmUuaGFuc2VuQGludGVs LmNvbT7CwXgEEwECACIFAlQ+9J0CGwMGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheAAAoJEGg1 lTBwyZKwLZUP/0dnbhDc229u2u6WtK1s1cSd9WsflGXGagkR6liJ4um3XCfYWDHvIdkHYC1t MNcVHFBwmQkawxsYvgO8kXT3SaFZe4ISfB4K4CL2qp4JO+nJdlFUbZI7cz/Td9z8nHjMcWYF IQuTsWOLs/LBMTs+ANumibtw6UkiGVD3dfHJAOPNApjVr+M0P/lVmTeP8w0uVcd2syiaU5jB aht9CYATn+ytFGWZnBEEQFnqcibIaOrmoBLu2b3fKJEd8Jp7NHDSIdrvrMjYynmc6sZKUqH2 I1qOevaa8jUg7wlLJAWGfIqnu85kkqrVOkbNbk4TPub7VOqA6qG5GCNEIv6ZY7HLYd/vAkVY E8Plzq/NwLAuOWxvGrOl7OPuwVeR4hBDfcrNb990MFPpjGgACzAZyjdmYoMu8j3/MAEW4P0z F5+EYJAOZ+z212y1pchNNauehORXgjrNKsZwxwKpPY9qb84E3O9KYpwfATsqOoQ6tTgr+1BR CCwP712H+E9U5HJ0iibN/CDZFVPL1bRerHziuwuQuvE0qWg0+0SChFe9oq0KAwEkVs6ZDMB2 P16MieEEQ6StQRlvy2YBv80L1TMl3T90Bo1UUn6ARXEpcbFE0/aORH/jEXcRteb+vuik5UGY 5TsyLYdPur3TXm7XDBdmmyQVJjnJKYK9AQxj95KlXLVO38lczsFNBFRjzmoBEACyAxbvUEhd GDGNg0JhDdezyTdN8C9BFsdxyTLnSH31NRiyp1QtuxvcqGZjb2trDVuCbIzRrgMZLVgo3upr MIOx1CXEgmn23Zhh0EpdVHM8IKx9Z7V0r+rrpRWFE8/wQZngKYVi49PGoZj50ZEifEJ5qn/H Nsp2+Y+bTUjDdgWMATg9DiFMyv8fvoqgNsNyrrZTnSgoLzdxr89FGHZCoSoAK8gfgFHuO54B lI8QOfPDG9WDPJ66HCodjTlBEr/Cwq6GruxS5i2Y33YVqxvFvDa1tUtl+iJ2SWKS9kCai2DR 3BwVONJEYSDQaven/EHMlY1q8Vln3lGPsS11vSUK3QcNJjmrgYxH5KsVsf6PNRj9mp8Z1kIG qjRx08+nnyStWC0gZH6NrYyS9rpqH3j+hA2WcI7De51L4Rv9pFwzp161mvtc6eC/GxaiUGuH BNAVP0PY0fqvIC68p3rLIAW3f97uv4ce2RSQ7LbsPsimOeCo/5vgS6YQsj83E+AipPr09Caj 0hloj+hFoqiticNpmsxdWKoOsV0PftcQvBCCYuhKbZV9s5hjt9qn8CE86A5g5KqDf83Fxqm/ vXKgHNFHE5zgXGZnrmaf6resQzbvJHO0Fb0CcIohzrpPaL3YepcLDoCCgElGMGQjdCcSQ+Ci FCRl0Bvyj1YZUql+ZkptgGjikQARAQABwsFfBBgBAgAJBQJUY85qAhsMAAoJEGg1lTBwyZKw l4IQAIKHs/9po4spZDFyfDjunimEhVHqlUt7ggR1Hsl/tkvTSze8pI1P6dGp2XW6AnH1iayn yRcoyT0ZJ+Zmm4xAH1zqKjWplzqdb/dO28qk0bPso8+1oPO8oDhLm1+tY+cOvufXkBTm+whm +AyNTjaCRt6aSMnA/QHVGSJ8grrTJCoACVNhnXg/R0g90g8iV8Q+IBZyDkG0tBThaDdw1B2l asInUTeb9EiVfL/Zjdg5VWiF9LL7iS+9hTeVdR09vThQ/DhVbCNxVk+DtyBHsjOKifrVsYep WpRGBIAu3bK8eXtyvrw1igWTNs2wazJ71+0z2jMzbclKAyRHKU9JdN6Hkkgr2nPb561yjcB8 sIq1pFXKyO+nKy6SZYxOvHxCcjk2fkw6UmPU6/j/nQlj2lfOAgNVKuDLothIxzi8pndB8Jju KktE5HJqUUMXePkAYIxEQ0mMc8Po7tuXdejgPMwgP7x65xtfEqI0RuzbUioFltsp1jUaRwQZ MTsCeQDdjpgHsj+P2ZDeEKCbma4m6Ez/YWs4+zDm1X8uZDkZcfQlD9NldbKDJEXLIjYWo1PH hYepSffIWPyvBMBTW2W5FRjJ4vLRrJSUoEfJuPQ3vW9Y73foyo/qFoURHO48AinGPZ7PC7TF vUaNOTjKedrqHkaOcqB185ahG2had0xnFsDPlx5y In-Reply-To: <20260630191350.3837-1-chang.seok.bae@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 6/30/26 12:13, Chang S. Bae wrote: > The MSR IA32_MCU_STATUS, if available, may report a partial update status > on a microcode update. This indicates that only a subset of microcode > components was updated successfully while other parts of updates failed, > which in turn leaves the system in an undefined and (potentially) > unreliable state. A modern individual microcode update update contains firmware for many pieces of silicon inside the CPU. Sometimes, a single update operation successfully updates some components and not others leaving a partially-applied update. This leaves the system in an undefined and unreliable state. > The status is possible on newer CPUs. While validation is expected to > prevent these error conditions in normal deployments, handling them > explicitly protects systems against an otherwise undefined state. I think that this is saying that CPUs try hard not to throw up their hands and give up mid-update. But, the world is hard and things don't always go to plan. > +#define MSR_IA32_MCU_STATUS 0x0000007c > +#define MCU_PARTIAL_UPDATE BIT(0) > +#define AUTH_FAIL_ON_MCU_COMPONENT BIT(1) Let's just make a : #define MCU_STATUS_FAILURE_MASK (MCU_PARTIAL_UPDATE \ AUTH_FAIL_ON_MCU_COMPONENT) > diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c > index f4a444e6114d..0b474a7c6986 100644 > --- a/arch/x86/kernel/cpu/microcode/intel.c > +++ b/arch/x86/kernel/cpu/microcode/intel.c > @@ -76,6 +76,9 @@ static struct microcode_intel *ucode_patch_late __read_mostly; > /* last level cache size per core */ > static unsigned int llc_size_per_core __ro_after_init; > > +/* CPU capability for update status and staging support */ > +static bool cpu_has_mcu __ro_after_init; These are *SUCH* slow, rare paths that I'm not even sure we need to cache this. > /* microcode format is extended from prescott processors */ > struct extended_signature { > unsigned int sig; > @@ -702,6 +705,16 @@ static enum ucode_state __apply_microcode(struct ucode_cpu_info *uci, > /* write microcode via MSR 0x79 */ > native_wrmsrq(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); > > + /* Check if the update put the system in an unreliable state */ > + if (cpu_has_mcu) { > + u64 status = native_rdmsrq(MSR_IA32_MCU_STATUS); > + > + if (status & (MCU_PARTIAL_UPDATE | AUTH_FAIL_ON_MCU_COMPONENT)) { > + pr_emerg("Partial update: MSR_IA32_MCU_STATUS=0x%llx\n", status); > + nmi_panic(NULL, "Microcode load: fatal status from partial update"); > + } > + } Are both messages needed? Is this because nmi_panic() doesn't do printk() formatting? Also, let's just say: nmi_panic(NULL, "Fatal microcode update failure"); > rev = intel_get_microcode_revision(); > if (rev != mc->hdr.rev) > return UCODE_ERROR; > @@ -779,11 +792,30 @@ static int __init save_builtin_microcode(void) > } > early_initcall(save_builtin_microcode); > > +#define CPUID_EDX_ARCH_CAP BIT(29) > + > +static __init bool mcu_capable(void) > +{ > + if (native_cpuid_eax(0) < 7) > + return false; > + > + if (!(native_cpuid_edx(7) & CPUID_EDX_ARCH_CAP)) > + return false; > + > + if (!(native_rdmsrq(MSR_IA32_ARCH_CAPABILITIES) & ARCH_CAP_MCU_ENUM)) > + return false; > + > + return true; > +} Comments, please. "mcu_capable" sounds like "Is this CPU capable of microcode updates", which doesn't seem quite right or logically sensible. Second, this needs to say why it's using raw CPUID functions and not X86_FEATURE* bits or cpuid(). > /* Load microcode on BSP from initrd or builtin blobs */ > void __init load_ucode_intel_bsp(struct early_load_data *ed) > { > struct ucode_cpu_info uci; > > + /* Indicate early enough to cover the early-loading path */ > + cpu_has_mcu = mcu_capable(); > + > uci.mc = get_microcode_blob(&uci, false); > ed->old_rev = uci.cpu_sig.rev; > > @@ -1023,8 +1055,7 @@ static __init bool staging_available(void) > { > u64 val; > > - val = x86_read_arch_cap_msr(); > - if (!(val & ARCH_CAP_MCU_ENUM)) > + if (!cpu_has_mcu) > return false; > > rdmsrq(MSR_IA32_MCU_ENUMERATION, val); Yeah, I'm not sure we need to cache mcu_capable(). Just call it twice.