From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36B8923C4E1; Thu, 12 Jun 2025 11:05:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749726355; cv=none; b=r0l8sLStE2BLys29Qgj/9I7n1XOsTxiPJDW6Z1G8vbebkoNy/B6Mo1jjGVb52ZmzMxz+ijzX0Fim9/TklXKNZEbPxFoLUmtT3SbWq9fnVmwZJu7nTyBq7B5rZ6B1Xuupcq/ehX/Br5kkOhKURYq/PMo/kgisLZL423mwFMu7NZ4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749726355; c=relaxed/simple; bh=J7zUfhMpAdwFfUP75/R8HkzXHrkbFmTeVwn8MXHX3wo=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=rt9r0YEEaCtllte0kd4Rt0aYY5By8lQ1TguGvIeVfBqy/CJ0Qo8jy1lN2argjzYsQSeVIJS7HHJr9MEHbUAWGwyGwK9TPsXha470o6MpE1v6/GHYJrk4fosduCsoHVk+tlVALq1HJYHmki3XEby6d7AnItXHz7u/UztVHOEjUgA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=G5BJuoTc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="G5BJuoTc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AFA18C4CEEA; Thu, 12 Jun 2025 11:05:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749726354; bh=J7zUfhMpAdwFfUP75/R8HkzXHrkbFmTeVwn8MXHX3wo=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=G5BJuoTc4SmTGNDTEXaxziELQuqow+YWxAYIBa3/bnaqCE15yWEFuB+v/S7567Gvd Es6LynGXcv5ll4OSjE7b0sk6pKbD4tcjBDTPMKy0m+gf8kBWR/FTNVY1UHRPM65bMt jmsBOplO9IAkKCWw3IIYTrg4EE1SZmPw3kvARLswbhZI1wwPsC9ByxfBscYrTvsDWY U20HQ4loBBP+hlcE3HQ17MbfgXB1G31CJveorWHgY5FV/+di1E7DxmFv8XsgB3/LVG caqfdKlvLBNYjRznPW9euvbbKUwZGxA0FIKed+mVcfm8SsxeNO4kCXn4mR5S9rOwYL xCMaGxB/I1bNA== Message-ID: <4f31f016-d250-41ea-b613-b074b8ea00d1@kernel.org> Date: Thu, 12 Jun 2025 13:05:49 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 5/9] ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp13 To: Clement LE GOFFIC , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Bartosz Golaszewski Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org References: <20250523-hdp-upstream-v3-0-bd6ca199466a@foss.st.com> <20250523-hdp-upstream-v3-5-bd6ca199466a@foss.st.com> <5b7a2102-ff68-4aab-a88d-0c4f9195ef95@kernel.org> <3c868c4b-8a0e-44b5-9d6e-3a0526d9deeb@foss.st.com> <3ba588ed-1614-4877-b6fc-b5aa853b8c2e@kernel.org> <714ad17d-53f1-4703-8e13-61c290a8da89@foss.st.com> <7000f63e-5e68-465d-9d7f-1a6ca0524222@kernel.org> <42a0b7ab-d85d-4d52-a263-4a4648c7ff05@kernel.org> <2865ab3a-1c20-4951-8132-4be98d73d70e@foss.st.com> <26a4f12a-2295-402e-8e31-45733aa6582d@foss.st.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 12/06/2025 11:31, Clement LE GOFFIC wrote: > On 6/11/25 17:48, Krzysztof Kozlowski wrote: >> On 11/06/2025 16:08, Clement LE GOFFIC wrote: >>> On 6/11/25 08:35, Krzysztof Kozlowski wrote: >>>> On 10/06/2025 15:33, Clement LE GOFFIC wrote: >>>>> On 6/10/25 14:38, Krzysztof Kozlowski wrote: >>>>>> On 10/06/2025 14:02, Clement LE GOFFIC wrote: >>>>>>> On 5/29/25 11:01, Krzysztof Kozlowski wrote: >>>>>>>> On 28/05/2025 14:14, Clement LE GOFFIC wrote: >>>>>>>>>> >>>>>>>>>>> + }; >>>>>>>>>>> + >>>>>>>>>>> + hdp: pinctrl@5002a000 { >>>>>>>>>>> + compatible = "st,stm32mp131-hdp"; >>>>>>>>>>> + reg = <0x5002a000 0x400>; >>>>>>>>>>> + clocks = <&rcc HDP>; >>>>>>>>>>> status = "disabled"; >>>>>>>>>> >>>>>>>>>> Why are you disabling it? What is missing? >>>>>>>>> >>>>>>>>> Nothing is missing just disabled by default. >>>>>>>>> The node is then enabled when needed in board's dts file. >>>>>>>> Nodes should not be disabled by default if they are complete. That's why >>>>>>>> I asked what is missing. Drop. >>>>>>> >>>>>>> Hi Krzysztof, OK I better understand now. >>>>>>> So yes the 'pinctrl-*' properties which are board dependent are lacking. >>>>>> >>>>>> These are not properties of this node. >>>>> >>>>> Does this mean I should add 'pinctrl-*' properties in bindings yaml file ? >>>>> I don't get it.. >>>> >>>> These properties have no meaning here, so the hardware description is >>>> complete. You claim that you miss them thus device is incomplete is just >>>> not correct: these properties do not belong here! They belong to the >>>> board but even there they are totally optional. Why would they be a >>>> required resource? >>>> >>>> To remind: we talk here ONLY about required resources. >>> >>> Yes, 'pinctrl-*' properties belongs to the board and are not required. >>> So nothing is missing. >>> >>> This hdp node in the SoC dtsi file can be enabled by default. >>> But the hdp driver will probe and do nothing because without the >>> 'pinctrl-*' properties from the board files it would not be able to >>> access to any pin. >> >> >> Pinctrl has other features in general, including interfaces to userspace >> (as pretty often combined with gpio, although not sure if relevant here). > > You're right. Also HDP pinctrl has a GPO feature accessible from userspace. > But by default the HDP is not connected to any pad; it needs the board OK, then that was the answer to my first question - what is missing. However aren't these pads connected internally also to other parts of the SoC (like in most other vendors)? > 'pinctrl-*' properties to configure the SoC pinctrl and expose HDP on > the SoC pads. > > That's why for me the enabling of the driver should be in the board file > together with the SoC pinctrl configuration. And what are the default pad settings configured by HPD driver in bootloader (and by bootloader I mean one of few bootloaders this is going to be used on like U-Boot) > > The userland cannot change the pinctrl alternate function mux, this is > statically defined by the devicetree. If you expose GPIO then userland needs this regardless of alternate mux. IOW, board level could not configure mux because it should be always configured to safe GPIO input. Best regards, Krzysztof