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From: Li Ming <ming.li@zohomail.com>
To: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Cc: Ard Biesheuvel <ardb@kernel.org>,
	Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Yazen Ghannam <yazen.ghannam@amd.com>,
	Terry Bowman <terry.bowman@amd.com>,
	linux-efi@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-cxl@vger.kernel.org
Subject: Re: [PATCH v8 2/2] cxl/pci: Add trace logging for CXL PCIe Port RAS errors
Date: Thu, 13 Mar 2025 09:03:48 +0800	[thread overview]
Message-ID: <4f4e317d-58b2-4059-b112-3c1b78318bbe@zohomail.com> (raw)
In-Reply-To: <20250310223839.31342-3-Smita.KoralahalliChannabasappa@amd.com>

On 3/11/2025 6:38 AM, Smita Koralahalli wrote:
> The CXL drivers use kernel trace functions for logging endpoint and
> Restricted CXL host (RCH) Downstream Port RAS errors. Similar functionality
> is required for CXL Root Ports, CXL Downstream Switch Ports, and CXL
> Upstream Switch Ports.
>
> Introduce trace logging functions for both RAS correctable and
> uncorrectable errors specific to CXL PCIe Ports. Use them to trace
> FW-First Protocol errors.
>
> Co-developed-by: Terry Bowman <terry.bowman@amd.com>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
> Reviewed-by: Ira Weiny <ira.weiny@intel.com>

Reviewed-by: Li Ming <ming.li@zohomail.com>


  parent reply	other threads:[~2025-03-13  1:04 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-10 22:38 [PATCH v8 0/2] acpi/ghes, cper, cxl: Process CXL CPER Protocol errors Smita Koralahalli
2025-03-10 22:38 ` [PATCH v8 1/2] acpi/ghes, cxl/pci: Process CXL CPER Protocol Errors Smita Koralahalli
2025-03-12 17:56   ` Ira Weiny
2025-03-12 18:58   ` Alison Schofield
2025-03-13  1:03   ` Li Ming
2025-03-10 22:38 ` [PATCH v8 2/2] cxl/pci: Add trace logging for CXL PCIe Port RAS errors Smita Koralahalli
2025-03-12 18:59   ` Alison Schofield
2025-03-13  1:03   ` Li Ming [this message]
2025-03-13 19:38 ` [PATCH v8 0/2] acpi/ghes, cper, cxl: Process CXL CPER Protocol errors Luck, Tony
2025-03-13 19:58 ` Dave Jiang

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