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Thu, 17 Sep 2026 15:26:02 -0700 (PDT) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: Frank Li , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: pierluigi.p@variscite.com, Stefano Radaelli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Nate Drude Subject: [PATCH v3 2/3] arm64: dts: imx8mm-var-dart: add TPM support Date: Fri, 18 Sep 2026 00:25:44 +0200 Message-ID: <4f550d729c32725e96884b4ee3d10afa908bb15f.1789683864.git.stefano.r@variscite.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Stefano Radaelli Add support for the TPM available on the Variscite DART-MX8M-MINI SOM. Co-developed-by: Nate Drude Signed-off-by: Nate Drude Signed-off-by: Stefano Radaelli --- v2->v3: - Fixed reset-gpio polarity v1->v2: - Add tpm pinctrl - Add comment on tpm reset line .../boot/dts/freescale/imx8mm-var-dart.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi index c7a9eb23e5e8..cb7998616a87 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi @@ -138,6 +138,16 @@ &i2c1 { sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; + st33ktpm2xi2c_som: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm_reset>; + label = "tpm"; + /* active-low TPM reset line. */ + reset-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; + }; + pmic@4b { compatible = "rohm,bd71847"; reg = <0x4b>; @@ -452,6 +462,12 @@ MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 >; }; + pinctrl_tpm_reset: tpm-resetgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x19 + >; + }; + pinctrl_uart4: uart4grp { fsl,pins = < MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x140 -- 2.47.3