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Thu, 06 Mar 2025 07:12:12 -0800 (PST) Message-ID: <4f91fe1c5eed00e58a3587bceaef3e5e2a1124cf.camel@linaro.org> Subject: Re: [PATCH v2 2/4] pinctrl: samsung: add dedicated SoC eint suspend/resume callbacks From: =?ISO-8859-1?Q?Andr=E9?= Draszik To: Peter Griffin , Krzysztof Kozlowski , Sylwester Nawrocki , Alim Akhtar , Linus Walleij Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, kernel-team@android.com, jaewon02.kim@samsung.com Date: Thu, 06 Mar 2025 15:12:11 +0000 In-Reply-To: References: <20250301-pinctrl-fltcon-suspend-v2-0-a7eef9bb443b@linaro.org> <20250301-pinctrl-fltcon-suspend-v2-2-a7eef9bb443b@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.53.2-1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Thu, 2025-03-06 at 11:57 +0000, Andr=C3=A9 Draszik wrote: > On Sat, 2025-03-01 at 11:43 +0000, Peter Griffin wrote: > > [...] > > =C2=A0 > > -static void exynos_pinctrl_resume_bank( > > - struct samsung_pinctrl_drv_data *drvdata, > > - struct samsung_pin_bank *bank) > > +void exynos_pinctrl_resume(struct samsung_pin_bank *bank) > > =C2=A0{ > > =C2=A0 struct exynos_eint_gpio_save *save =3D bank->soc_priv; > > =C2=A0 void __iomem *regs =3D bank->eint_base; > > =C2=A0 > > - if (clk_enable(bank->drvdata->pclk)) { > > - dev_err(bank->gpio_chip.parent, > > - "unable to enable clock for restoring state\n"); > > - return; > > + if (bank->eint_type =3D=3D EINT_TYPE_GPIO) { > > + pr_debug("%s:=C2=A0=C2=A0=C2=A0=C2=A0 con %#010x =3D> %#010x\n", ban= k->name, > > + readl(regs + EXYNOS_GPIO_ECON_OFFSET > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 + bank->eint_offset), save->ei= nt_con); > > + pr_debug("%s: fltcon0 %#010x =3D> %#010x\n", bank->name, > > + readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 + 2 * bank->eint_offset), save= ->eint_fltcon0); > > + pr_debug("%s: fltcon1 %#010x =3D> %#010x\n", bank->name, > > + readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 + 2 * bank->eint_offset + 4), > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 save->eint_fltcon1); The indent on this last line is a bit off. > > + pr_debug("%s:=C2=A0=C2=A0=C2=A0 mask %#010x =3D> %#010x\n", bank->na= me, > > + readl(regs + bank->irq_chip->eint_mask > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 + bank->eint_offset), save->ei= nt_mask); > > + > > + writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 + bank->eint_offset); > > + writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 + 2 * bank->eint_offset); > > + writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 + 2 * bank->eint_offset + 4); > > + writel(save->eint_mask, regs + bank->irq_chip->eint_mask > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 + bank->eint_offset); > > =C2=A0 } > > - > > - pr_debug("%s:=C2=A0=C2=A0=C2=A0=C2=A0 con %#010x =3D> %#010x\n", bank= ->name, > > - readl(regs + EXYNOS_GPIO_ECON_OFFSET > > - + bank->eint_offset), save->eint_con); > > - pr_debug("%s: fltcon0 %#010x =3D> %#010x\n", bank->name, > > - readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET > > - + 2 * bank->eint_offset), save->eint_fltcon0); > > - pr_debug("%s: fltcon1 %#010x =3D> %#010x\n", bank->name, > > - readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET > > - + 2 * bank->eint_offset + 4), save->eint_fltcon1); > > - pr_debug("%s:=C2=A0=C2=A0=C2=A0 mask %#010x =3D> %#010x\n", bank->nam= e, > > - readl(regs + bank->irq_chip->eint_mask > > - + bank->eint_offset), save->eint_mask); > > - > > - writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET > > - + bank->eint_offset); > > - writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET > > - + 2 * bank->eint_offset); > > - writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET > > - + 2 * bank->eint_offset + 4); > > - writel(save->eint_mask, regs + bank->irq_chip->eint_mask > > - + bank->eint_offset); > > - > > - clk_disable(bank->drvdata->pclk); > > =C2=A0} > > =C2=A0 > > -static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_= data *drvdata, > > - =C2=A0=C2=A0 struct samsung_pin_bank *bank) > > +void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank) > > =C2=A0{ > > =C2=A0 struct exynos_eint_gpio_save *save =3D bank->soc_priv; > > =C2=A0 void __iomem *regs =3D bank->eint_base; > > =C2=A0 > > - if (clk_enable(bank->drvdata->pclk)) { > > - dev_err(bank->gpio_chip.parent, > > - "unable to enable clock for restoring state\n"); > > - return; > > + if (bank->eint_type =3D=3D EINT_TYPE_GPIO) { > > + /* exynosautov920 has eint_con_offset for all but one bank */ > > + if (!bank->eint_con_offset) > > + exynos_pinctrl_resume(bank); > > + > > + pr_debug("%s:=C2=A0=C2=A0=C2=A0=C2=A0 con %#010x =3D> %#010x\n", ban= k->name, > > + readl(regs + bank->pctl_offset + bank->eint_con_offset), > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 save->eint_con); and here Cheers, Andre'