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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6248711bfe8sm5192325a12.20.2025.09.08.09.22.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Sep 2025 09:22:08 -0700 (PDT) Message-ID: <4fa44ec5-2792-45e3-af87-b3e4d2ed5d86@oss.qualcomm.com> Date: Mon, 8 Sep 2025 18:22:05 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU To: Akhil P Oommen , Dmitry Baryshkov Cc: Neil Armstrong , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20250725-topic-x1e80100-gpu-bwvote-v2-1-58d2fbb6a127@linaro.org> <33442cc4-a205-46a8-a2b8-5c85c236c8d4@oss.qualcomm.com> <269506b6-f51b-45cc-b7cc-7ad0e5ceea47@linaro.org> <1727374d-0461-4442-ab35-9acb8ef7f666@oss.qualcomm.com> <77db4861-4868-4110-8c31-eb2045ddbf4b@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <77db4861-4868-4110-8c31-eb2045ddbf4b@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAzOCBTYWx0ZWRfXykMR74gN/sxs P/T8FAzY1F2qkD7/OlwD/NB8saHJejhjUhVy3ehIfQSMIvieNy/YTPMfBAHr5Y4BV7TJy9x67QJ TT+UR6b3USeeq5aG7CQhsIgrHglc06I3zjeD04ZLCHUmfBHzWch9xiWHCn7yQwZEWWsbEPbPrRF XVRY40TNBznda4SvAUzNGMn23yl6oDpXGeKnVdpWNskAlolm7CZ9UCikE8i4keVlKLuf2DwmWLw t714ZNQaHKLdYwav4nrijJtGTlMFXBGNnzqUlgOlpZgRmMdiFX6XlUnlzdrWvYCkcmcBFZP57RS TF+WPbMtts1XJZjl1KFyx65rc/5IzWsPGG1geC1P25DFd4RTGfWdioS3pX03eK+gPKPz2kGxrZ5 1UwD/3fW X-Authority-Analysis: v=2.4 cv=J66q7BnS c=1 sm=1 tr=0 ts=68bf02b3 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=-rBNSpjuQUH0YdP2-XMA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: eR7PIJwI080nSmHQi-AAig4V9YPVYReV X-Proofpoint-ORIG-GUID: eR7PIJwI080nSmHQi-AAig4V9YPVYReV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 clxscore=1015 spamscore=0 phishscore=0 adultscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060038 On 8/18/25 9:17 AM, Akhil P Oommen wrote: > On 8/16/2025 3:45 AM, Dmitry Baryshkov wrote: >> On Thu, Aug 14, 2025 at 07:52:13PM +0200, Konrad Dybcio wrote: >>> On 8/14/25 6:38 PM, Akhil P Oommen wrote: >>>> On 8/14/2025 7:56 PM, Neil Armstrong wrote: >>>>> Hi, >>>>> >>>>> On 14/08/2025 13:22, Konrad Dybcio wrote: >>>>>> On 8/14/25 1:21 PM, Konrad Dybcio wrote: >>>>>>> On 7/31/25 12:19 PM, Konrad Dybcio wrote: >>>>>>>> On 7/25/25 10:35 AM, Neil Armstrong wrote: >>>>>>>>> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth >>>>>>>>> along >>>>>>>>> the Frequency and Power Domain level, but by default we leave the >>>>>>>>> OPP core scale the interconnect ddr path. >>>>>>>>> >>>>>>>>> Declare the Bus Control Modules (BCMs) and the corresponding >>>>>>>>> parameters >>>>>>>>> in the GPU info struct to allow the GMU to vote for the bandwidth. >>>>>>>>> >>>>>>>>> Reviewed-by: Dmitry Baryshkov >>>>>>>>> Signed-off-by: Neil Armstrong >>>>>>>>> --- >>>>>>>>> Changes in v2: >>>>>>>>> - Used proper ACV perfmode bit/freq >>>>>>>>> - Link to v1: https://lore.kernel.org/r/20250721-topic-x1e80100- >>>>>>>>> gpu-bwvote-v1-1-946619b0f73a@linaro.org >>>>>>>>> --- >>>>>>>>>   drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++ >>>>>>>>>   1 file changed, 11 insertions(+) >>>>>>>>> >>>>>>>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/ >>>>>>>>> gpu/drm/msm/adreno/a6xx_catalog.c >>>>>>>>> index >>>>>>>>> 00e1afd46b81546eec03e22cda9e9a604f6f3b60..892f98b1f2ae582268adebd758437ff60456cdd5 100644 >>>>>>>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>>>>>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>>>>>>> @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = { >>>>>>>>>               .pwrup_reglist = &a7xx_pwrup_reglist, >>>>>>>>>               .gmu_chipid = 0x7050001, >>>>>>>>>               .gmu_cgc_mode = 0x00020202, >>>>>>>>> +            .bcms = (const struct a6xx_bcm[]) { >>>>>>>>> +                { .name = "SH0", .buswidth = 16 }, >>>>>>>>> +                { .name = "MC0", .buswidth = 4 }, >>>>>>>>> +                { >>>>>>>>> +                    .name = "ACV", >>>>>>>>> +                    .fixed = true, >>>>>>>>> +                    .perfmode = BIT(3), >>>>>>>>> +                    .perfmode_bw = 16500000, >>>>>>>> >>>>>>>> Reviewed-by: Konrad Dybcio >>>>>>> >>>>>>> Actually no, BIT(3) is for the CPU (OS), GPU should use BIT(2) >>>> >>>> You are right that BIT(2) is GPU specific, but that support was >>>> commercialized from A7XX_GEN3. Anyway, the Win KMD uses BIT(2), so lets >>>> use that in Linux too. >>>> >>>> I know some docs show BIT(2) support, but lets not bring in untested >>>> configurations. >>> >>> Eh, then let's get the docs fixed if you don't trust them because we can't >>> work like that.. >>> >>> FWIW this is information from per-platform RPMh cmd-db data >> >> If it comes from cmd-db, then we should be requesting it from the cmd-db >> driver rather than hardcoding it here. No, what I meant is that there is a piece of configuration that reflects what goes into cmd-db as its compiled and that's where I found that information > > Not really. This should be under the control of GPU driver. > BIT(3) is correct for X1E. BIT(3) is for APPS, see the interconnect driver which also uses it. This will create conflicts and may cause unvotes when some other driver requests perf_mode through the ICC API, but the GPU is sitting idle. Konrad