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([2601:586:5000:570:aad6:acd8:4ed9:299b]) by smtp.gmail.com with ESMTPSA id k3-20020a05620a414300b006ee7e223bb8sm2836373qko.39.2022.11.04.05.45.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 04 Nov 2022 05:45:57 -0700 (PDT) Message-ID: <4fd9dabb-c8f3-b826-2eb2-ab8b5816102a@linaro.org> Date: Fri, 4 Nov 2022 08:45:55 -0400 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH 3/4] arm64: dts: fsd: Add Ethernet support for FSYS0 Block of FSD SoC To: Sriranjani P , peppe.cavallaro@st.com, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, richardcochran@gmail.com Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, Pankaj Dubey , Jayati Sahu References: <20221104120517.77980-1-sriranjani.p@samsung.com> <20221104120517.77980-4-sriranjani.p@samsung.com> Content-Language: en-US From: Krzysztof Kozlowski In-Reply-To: <20221104120517.77980-4-sriranjani.p@samsung.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 04/11/2022 08:05, Sriranjani P wrote: > The FSD SoC contains two instances of Synopsys DWC QoS Ethernet IP, one > in FSYS0 block and other in PERIC block. > > Adds device tree node for Ethernet in FSYS0 Block and enables the same for > FSD platform. > > Cc: Rob Herring > Cc: Krzysztof Kozlowski > Cc: Richard Cochran > Cc: devicetree@vger.kernel.org > Signed-off-by: Pankaj Dubey > Signed-off-by: Jayati Sahu > Signed-off-by: Sriranjani P > --- > arch/arm64/boot/dts/tesla/fsd-evb.dts | 9 ++++ > arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 56 ++++++++++++++++++++++ > arch/arm64/boot/dts/tesla/fsd.dtsi | 38 +++++++++++++++ > 3 files changed, 103 insertions(+) > > diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts > index 1db6ddf03f01..42bf25c680e2 100644 > --- a/arch/arm64/boot/dts/tesla/fsd-evb.dts > +++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts > @@ -30,6 +30,15 @@ > }; > }; > > +ðernet_0 { > + status = "okay"; > + > + fixed-link { > + speed=<1000>; Missing spaces around =. > + full-duplex; > + }; > +}; > + > &fin_pll { > clock-frequency = <24000000>; > }; > diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi > index d0abb9aa0e9e..8c7e43085a2b 100644 > --- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi > +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi > @@ -64,6 +64,62 @@ > samsung,pin-pud = ; > samsung,pin-drv = ; > }; > + > + eth0_tx_clk: eth0-tx-clk-pins { > + samsung,pins = "gpf0-0"; > + samsung,pin-function = ; > + samsung,pin-pud = ; > + samsung,pin-drv = ; > + }; > + > + eth0_tx_data: eth0-tx-data-pins { > + samsung,pins = "gpf0-1", "gpf0-2", "gpf0-3", "gpf0-4"; > + samsung,pin-function = ; > + samsung,pin-pud = ; > + samsung,pin-drv = ; > + }; > + > + eth0_tx_ctrl: eth0-tx-ctrl-pins { > + samsung,pins = "gpf0-5"; > + samsung,pin-function = ; > + samsung,pin-pud = ; > + samsung,pin-drv = ; > + }; > + > + eth0_phy_intr: eth0-phy-intr-pins { > + samsung,pins = "gpf0-6"; > + samsung,pin-function = ; > + samsung,pin-pud = ; > + samsung,pin-drv = ; > + }; > + > + eth0_rx_clk: eth0-rx-clk-pins { > + samsung,pins = "gpf1-0"; > + samsung,pin-function = ; > + samsung,pin-pud = ; > + samsung,pin-drv = ; > + }; > + > + eth0_rx_data: eth0-rx-data-pins { > + samsung,pins = "gpf1-1", "gpf1-2", "gpf1-3", "gpf1-4"; > + samsung,pin-function = ; > + samsung,pin-pud = ; > + samsung,pin-drv = ; > + }; > + > + eth0_rx_ctrl: eth0-rx-ctrl-pins { > + samsung,pins = "gpf1-5"; > + samsung,pin-function = ; > + samsung,pin-pud = ; > + samsung,pin-drv = ; > + }; > + > + eth0_mdio: eth0-mdio-pins { > + samsung,pins = "gpf1-6", "gpf1-7"; > + samsung,pin-function = ; > + samsung,pin-pud = ; > + samsung,pin-drv = ; > + }; > }; > > &pinctrl_peric { > diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi > index f35bc5a288c2..2495928b71dc 100644 > --- a/arch/arm64/boot/dts/tesla/fsd.dtsi > +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi > @@ -32,6 +32,7 @@ > spi0 = &spi_0; > spi1 = &spi_1; > spi2 = &spi_2; > + eth0 = ðernet_0; Not every board will have ethernet, so this should be in board DTS. However other question is - why do you need it? > }; > > cpus { > @@ -860,6 +861,43 @@ > clocks = <&clock_fsys0 UFS0_MPHY_REFCLK_IXTAL26>; > clock-names = "ref_clk"; > }; > + > + ethernet_0: ethernet@15300000 { > + compatible = "tesla,dwc-qos-ethernet-4.21"; > + reg = <0x0 0x15300000 0x0 0x10000>; > + interrupts = ; > + clocks = > + /* ptp ref clock */ That's not a formatting used in sources. I doubt that they are actually useful as you copy the name of the clock. > + <&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I>, > + /* aclk clocks */ > + <&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I>, > + /* hclk clocks */ > + <&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I>, > + /* rgmii clocks */ > + <&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I>, > + /* rxi clocks */ > + <&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I>; > + clock-names = > + /* ptp ref clocks */ > + "ptp_ref", > + /* aclk clocks */ > + "master_bus", > + /* hclk clocks */ > + "slave_bus", > + /* rgmii clk */ > + "tx", > + /* rxi clocks */ > + "rx"; > + pinctrl-names = "default"; > + pinctrl-0 = <ð0_tx_clk>, <ð0_tx_data>, <ð0_tx_ctrl>, > + <ð0_phy_intr>, <ð0_rx_clk>, <ð0_rx_data>, > + <ð0_rx_ctrl>, <ð0_mdio>; > + local-mac-address = [45 54 48 30 4d 43]; So all devices in the world will have exactly the same MAC address? I don't think that's desired :) > + rx-clock-skew = <&sysreg_fsys0 0x0 0x2>; Where is the property documented? Does not look like you tested the DTS against bindings. Please run `make dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst for instructions). Please confirm that you perform above. > + iommus = <&smmu_fsys0 0x0 0x1>; > + status = "disabled"; Status is last. > + phy-mode = "rgmii"; > + }; > }; > }; > Best regards, Krzysztof