From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: forbidden405@outlook.com, Wei Xu <xuwei5@hisilicon.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Jiancheng Xue <xuejiancheng@hisilicon.com>,
Alex Elder <elder@linaro.org>,
Peter Griffin <peter.griffin@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 3/3] arm64: dts: hi3798cv200: add cache info
Date: Mon, 19 Feb 2024 08:20:58 +0100 [thread overview]
Message-ID: <4fdc2853-91f9-4b02-bfd6-68874baf1e9d@linaro.org> (raw)
In-Reply-To: <20240218-cache-v2-3-1fd919e2bd3e@outlook.com>
On 18/02/2024 13:02, Yang Xiwen via B4 Relay wrote:
> From: Yang Xiwen <forbidden405@outlook.com>
>
> During boot, the kernel complains:
>
> [ 0.044029] cacheinfo: Unable to detect cache hierarchy for CPU 0
>
> So add L1/L2 cache info to the dts according to the datasheet. (32KiB L1
> i-cache + 32 KiB L1 d-cache + 512 KiB L2 unified cache)
> cpu@3 {
> @@ -52,9 +73,25 @@ cpu@3 {
> device_type = "cpu";
> reg = <0x0 0x3>;
> enable-method = "psci";
> + d-cache-size = <0x8000>; /* 32 KiB */
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0x8000>; /* 32 KiB */
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + next-level-cache = <&L2_0>;
> };
> };
>
> + L2_0: l2-cache0 {
Do you have more than one? If not, then "l2-cache". If yes, then
"l2-cache-0".
Best regards,
Krzysztof
prev parent reply other threads:[~2024-02-19 7:21 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-18 12:02 [PATCH v2 0/3] arm64: dts: hi3798cv200: fix GICR size, add cache info, maintenance irq and GICH, GICV spaces Yang Xiwen via B4 Relay
2024-02-18 12:02 ` [PATCH v2 1/3] arm64: dts: hi3798cv200: fix the size of GICR Yang Xiwen via B4 Relay
2024-02-18 12:02 ` [PATCH v2 2/3] arm64: dts: hi3798cv200: add GICH, GICV register space and irq Yang Xiwen via B4 Relay
2024-02-18 12:02 ` [PATCH v2 3/3] arm64: dts: hi3798cv200: add cache info Yang Xiwen via B4 Relay
2024-02-19 7:20 ` Krzysztof Kozlowski [this message]
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