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[92.26.98.202]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c301a7225sm4452230f8f.26.2025.04.04.07.16.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 04 Apr 2025 07:16:14 -0700 (PDT) Message-ID: <4fff7dd0-70e4-4ec8-9ca7-7f7c52382d51@citrix.com> Date: Fri, 4 Apr 2025 15:16:13 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] x86/idle: Remove MFENCEs for X86_BUG_CLFLUSH_MONITOR To: Uros Bizjak , LKML Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" References: <20250402172458.1378112-1-andrew.cooper3@citrix.com> <1640cf43-8125-a562-91f9-9b306b863dc7@gmail.com> Content-Language: en-GB From: Andrew Cooper Autocrypt: addr=andrew.cooper3@citrix.com; keydata= xsFNBFLhNn8BEADVhE+Hb8i0GV6mihnnr/uiQQdPF8kUoFzCOPXkf7jQ5sLYeJa0cQi6Penp VtiFYznTairnVsN5J+ujSTIb+OlMSJUWV4opS7WVNnxHbFTPYZVQ3erv7NKc2iVizCRZ2Kxn srM1oPXWRic8BIAdYOKOloF2300SL/bIpeD+x7h3w9B/qez7nOin5NzkxgFoaUeIal12pXSR Q354FKFoy6Vh96gc4VRqte3jw8mPuJQpfws+Pb+swvSf/i1q1+1I4jsRQQh2m6OTADHIqg2E ofTYAEh7R5HfPx0EXoEDMdRjOeKn8+vvkAwhviWXTHlG3R1QkbE5M/oywnZ83udJmi+lxjJ5 YhQ5IzomvJ16H0Bq+TLyVLO/VRksp1VR9HxCzItLNCS8PdpYYz5TC204ViycobYU65WMpzWe LFAGn8jSS25XIpqv0Y9k87dLbctKKA14Ifw2kq5OIVu2FuX+3i446JOa2vpCI9GcjCzi3oHV e00bzYiHMIl0FICrNJU0Kjho8pdo0m2uxkn6SYEpogAy9pnatUlO+erL4LqFUO7GXSdBRbw5 gNt25XTLdSFuZtMxkY3tq8MFss5QnjhehCVPEpE6y9ZjI4XB8ad1G4oBHVGK5LMsvg22PfMJ ISWFSHoF/B5+lHkCKWkFxZ0gZn33ju5n6/FOdEx4B8cMJt+cWwARAQABzSlBbmRyZXcgQ29v cGVyIDxhbmRyZXcuY29vcGVyM0BjaXRyaXguY29tPsLBegQTAQgAJAIbAwULCQgHAwUVCgkI CwUWAgMBAAIeAQIXgAUCWKD95wIZAQAKCRBlw/kGpdefoHbdD/9AIoR3k6fKl+RFiFpyAhvO 59ttDFI7nIAnlYngev2XUR3acFElJATHSDO0ju+hqWqAb8kVijXLops0gOfqt3VPZq9cuHlh IMDquatGLzAadfFx2eQYIYT+FYuMoPZy/aTUazmJIDVxP7L383grjIkn+7tAv+qeDfE+txL4 SAm1UHNvmdfgL2/lcmL3xRh7sub3nJilM93RWX1Pe5LBSDXO45uzCGEdst6uSlzYR/MEr+5Z JQQ32JV64zwvf/aKaagSQSQMYNX9JFgfZ3TKWC1KJQbX5ssoX/5hNLqxMcZV3TN7kU8I3kjK mPec9+1nECOjjJSO/h4P0sBZyIUGfguwzhEeGf4sMCuSEM4xjCnwiBwftR17sr0spYcOpqET ZGcAmyYcNjy6CYadNCnfR40vhhWuCfNCBzWnUW0lFoo12wb0YnzoOLjvfD6OL3JjIUJNOmJy RCsJ5IA/Iz33RhSVRmROu+TztwuThClw63g7+hoyewv7BemKyuU6FTVhjjW+XUWmS/FzknSi dAG+insr0746cTPpSkGl3KAXeWDGJzve7/SBBfyznWCMGaf8E2P1oOdIZRxHgWj0zNr1+ooF /PzgLPiCI4OMUttTlEKChgbUTQ+5o0P080JojqfXwbPAyumbaYcQNiH1/xYbJdOFSiBv9rpt TQTBLzDKXok86M7BTQRS4TZ/ARAAkgqudHsp+hd82UVkvgnlqZjzz2vyrYfz7bkPtXaGb9H4 Rfo7mQsEQavEBdWWjbga6eMnDqtu+FC+qeTGYebToxEyp2lKDSoAsvt8w82tIlP/EbmRbDVn 7bhjBlfRcFjVYw8uVDPptT0TV47vpoCVkTwcyb6OltJrvg/QzV9f07DJswuda1JH3/qvYu0p vjPnYvCq4NsqY2XSdAJ02HrdYPFtNyPEntu1n1KK+gJrstjtw7KsZ4ygXYrsm/oCBiVW/OgU g/XIlGErkrxe4vQvJyVwg6YH653YTX5hLLUEL1NS4TCo47RP+wi6y+TnuAL36UtK/uFyEuPy wwrDVcC4cIFhYSfsO0BumEI65yu7a8aHbGfq2lW251UcoU48Z27ZUUZd2Dr6O/n8poQHbaTd 6bJJSjzGGHZVbRP9UQ3lkmkmc0+XCHmj5WhwNNYjgbbmML7y0fsJT5RgvefAIFfHBg7fTY/i kBEimoUsTEQz+N4hbKwo1hULfVxDJStE4sbPhjbsPCrlXf6W9CxSyQ0qmZ2bXsLQYRj2xqd1 bpA+1o1j2N4/au1R/uSiUFjewJdT/LX1EklKDcQwpk06Af/N7VZtSfEJeRV04unbsKVXWZAk uAJyDDKN99ziC0Wz5kcPyVD1HNf8bgaqGDzrv3TfYjwqayRFcMf7xJaL9xXedMcAEQEAAcLB XwQYAQgACQUCUuE2fwIbDAAKCRBlw/kGpdefoG4XEACD1Qf/er8EA7g23HMxYWd3FXHThrVQ HgiGdk5Yh632vjOm9L4sd/GCEACVQKjsu98e8o3ysitFlznEns5EAAXEbITrgKWXDDUWGYxd pnjj2u+GkVdsOAGk0kxczX6s+VRBhpbBI2PWnOsRJgU2n10PZ3mZD4Xu9kU2IXYmuW+e5KCA vTArRUdCrAtIa1k01sPipPPw6dfxx2e5asy21YOytzxuWFfJTGnVxZZSCyLUO83sh6OZhJkk b9rxL9wPmpN/t2IPaEKoAc0FTQZS36wAMOXkBh24PQ9gaLJvfPKpNzGD8XWR5HHF0NLIJhgg 4ZlEXQ2fVp3XrtocHqhu4UZR4koCijgB8sB7Tb0GCpwK+C4UePdFLfhKyRdSXuvY3AHJd4CP 4JzW0Bzq/WXY3XMOzUTYApGQpnUpdOmuQSfpV9MQO+/jo7r6yPbxT7CwRS5dcQPzUiuHLK9i nvjREdh84qycnx0/6dDroYhp0DFv4udxuAvt1h4wGwTPRQZerSm4xaYegEFusyhbZrI0U9tJ B8WrhBLXDiYlyJT6zOV2yZFuW47VrLsjYnHwn27hmxTC/7tvG3euCklmkn9Sl9IAKFu29RSo d5bD8kMSCYsTqtTfT6W4A3qHGvIDta3ptLYpIAOD2sY3GYq2nf3Bbzx81wZK14JdDDHUX2Rs 6+ahAA== In-Reply-To: <1640cf43-8125-a562-91f9-9b306b863dc7@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 04/04/2025 3:14 pm, Uros Bizjak wrote: > > > On 2. 04. 25 19:24, Andrew Cooper wrote: >> Commit 7e98b7192046 ("x86, idle: Use static_cpu_has() for CLFLUSH >> workaround, add barriers") adds barriers, justified with: >> >>    ... and add memory barriers around it since the documentation is >> explicit >>    that CLFLUSH is only ordered with respect to MFENCE. >> >> This also triggered the same adjustment in commit >> f8e617f45829 ("sched/idle/x86: Optimize unnecessary mwait_idle() resched >> IPIs") during development, although it failed to get the >> static_cpu_has_bug() >> treatment. >> >> X86_BUG_CLFLUSH_MONITOR (a.k.a the AAI65 errata) is specific to Intel >> CPUs, >> and the SDM currently states: >> >>    Executions of the CLFLUSH instruction are ordered with respect to >> each >>    other and with respect to writes, locked read-modify-write >> instructions, >>    and fence instructions[1]. >> >> With footnote 1 reading: >> >>    Earlier versions of this manual specified that executions of the >> CLFLUSH >>    instruction were ordered only by the MFENCE instruction.  All >> processors >>    implementing the CLFLUSH instruction also order it relative to the >> other >>    operations enumerated above. >> >> i.e. The SDM was incorrect at the time, and barriers should not have >> been >> inserted.  Double checking the original AAI65 errata (not available from >> intel.com any more) shows no mention of barriers either. >> >> Note: If this were a general codepath, the MFENCEs would be needed, >> because >>        AMD CPUs of the same vintage do sport otherwise-unordered >> CLFLUSHs. >> >> Furthermore, use a plain alternative, rather than >> static_cpu_has_bug() and/or >> no optimisation.  The workaround is a single instruction. >> >> Use an explicit %rax pointer rather than a general memory operand, >> because >> MONITOR takes the pointer implicitly in the same way. >> >> Link: >> https://web.archive.org/web/20090219054841/http://download.intel.com/design/xeon/specupdt/32033601.pdf >> Fixes: 7e98b7192046 ("x86, idle: Use static_cpu_has() for CLFLUSH >> workaround, add barriers") >> Fixes: f8e617f45829 ("sched/idle/x86: Optimize unnecessary >> mwait_idle() resched IPIs") >> Signed-off-by: Andrew Cooper >> --- >> CC: Thomas Gleixner >> CC: Ingo Molnar >> CC: Borislav Petkov >> CC: Dave Hansen >> CC: x86@kernel.org >> CC: "H. Peter Anvin" >> CC: linux-kernel@vger.kernel.org >> >> v2: >>   * Fix the same pattern in mwait_idle() too >>   * Expand on why we're not using a general memory operand. >> --- >>   arch/x86/include/asm/mwait.h | 11 +++++------ >>   arch/x86/kernel/process.c    | 10 ++++------ >>   2 files changed, 9 insertions(+), 12 deletions(-) > > There is another instance of the same sequence in > arch/x86/kernel/smpboot.c: > >         /* >          * The CLFLUSH is a workaround for erratum AAI65 for >          * the Xeon 7400 series.  It's not clear it is actually >          * needed, but it should be harmless in either case. >          * The WBINVD is insufficient due to the spurious-wakeup >          * case where we return around the loop. >          */ >         mb(); >         clflush(md); >         mb(); >         __monitor(md, 0, 0); >         mb(); >         __mwait(eax_hint, 0); > > Should this also be converted to the new sequence? Yes, it ought to. I'm OoO for a while though.  If you fancy doing a patch, please go ahead.  Or a maintainer could fold a 3rd hunk into this patch? ~Andrew