From: Jiang Liu <jiang.liu@huawei.com>
To: "Kaneshige, Kenji" <kaneshige.kenji@jp.fujitsu.com>
Cc: Jiang Liu <liuj97@gmail.com>, Bjorn Helgaas <bhelgaas@google.com>,
Don Dutile <ddutile@redhat.com>, Yinghai Lu <yinghai@kernel.org>,
"Izumi, Taku" <izumi.taku@jp.fujitsu.com>,
"Rafael J . Wysocki" <rjw@sisk.pl>,
Yijing Wang <wangyijing@huawei.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>
Subject: Re: [RFC PATCH v2 07/32] PCI/portdrv: use PCIe capabilities access functions to simplify implementation
Date: Wed, 25 Jul 2012 17:44:49 +0800 [thread overview]
Message-ID: <500FC011.5050807@huawei.com> (raw)
In-Reply-To: <4A338DB2991D2A44B9A44B8718AECF650A4586BC@G01JPEXMBYT03>
>> diff --git a/drivers/pci/pcie/portdrv_core.c
>> b/drivers/pci/pcie/portdrv_core.c
>> index bf320a9..37bff83 100644
>> --- a/drivers/pci/pcie/portdrv_core.c
>> +++ b/drivers/pci/pcie/portdrv_core.c
>> @@ -76,7 +76,6 @@ static int pcie_port_enable_msix(struct pci_dev *dev,
>> int *vectors, int mask)
>> struct msix_entry *msix_entries;
>> int idx[PCIE_PORT_DEVICE_MAXSERVICES];
>> int nr_entries, status, pos, i, nvec;
>> - u16 reg16;
>> u32 reg32;
>>
>> nr_entries = pci_msix_table_size(dev);
>> @@ -120,9 +119,7 @@ static int pcie_port_enable_msix(struct pci_dev *dev,
>> int *vectors, int mask)
>> * the value in this field indicates which MSI-X Table entry
>> is
>> * used to generate the interrupt message."
>> */
>> - pos = pci_pcie_cap(dev);
>> - pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16);
>> - entry = (reg16 & PCI_EXP_FLAGS_IRQ) >> 9;
>> + entry = (dev->pcie_flags_reg & PCI_EXP_FLAGS_IRQ) >> 9;
>> if (entry >= nr_entries)
>> goto Error;
>
> I think we need to use pci_read_config_word() for MSI setup.
>
> "Interrupt Message Number" in the PCIe capability register can vary depending
> on whether MSI or MSI-x is enabled. Please see PCIe spec for details.
>
> Could you double-check that?
>
> Regards,
> Kenji Kaneshige
Good catch, will revert this change.
Thanks!
Gerry
next prev parent reply other threads:[~2012-07-25 9:46 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-07-24 16:31 [RFC PATCH v2 00/32] provide interfaces to access PCIe capabilities registers Jiang Liu
2012-07-24 16:31 ` [RFC PATCH v2 01/32] PCI: add pcie_flags_reg into struct pci_dev to cache PCIe capabilities register Jiang Liu
2012-07-25 15:12 ` Don Dutile
2012-07-26 13:47 ` Yijing Wang
2012-07-24 16:31 ` [RFC PATCH v2 02/32] PCI: introduce pci_pcie_type(dev) to replace pci_dev->pcie_type Jiang Liu
2012-07-24 16:31 ` [RFC PATCH v2 03/32] PCI: remove unused field pcie_type from struct pci_dev Jiang Liu
2012-07-24 16:31 ` [RFC PATCH v2 04/32] PCI: add PCIe capabilities access functions to hide differences among PCIe specs Jiang Liu
2012-07-24 21:12 ` Don Dutile
2012-07-29 16:22 ` Jiang Liu
2012-07-24 16:31 ` [RFC PATCH v2 05/32] PCI/core: use PCIe capabilities access functions to simplify implementation Jiang Liu
2012-07-25 21:12 ` Don Dutile
2012-07-29 2:12 ` Jiang Liu
2012-07-24 16:31 ` [RFC PATCH v2 06/32] PCI/hotplug: " Jiang Liu
2012-07-24 16:31 ` [RFC PATCH v2 07/32] PCI/portdrv: " Jiang Liu
2012-07-25 5:51 ` Kaneshige, Kenji
2012-07-25 9:44 ` Jiang Liu [this message]
2012-07-24 16:31 ` [RFC PATCH v2 08/32] PCI/pciehp: " Jiang Liu
2012-07-24 16:31 ` [RFC PATCH v2 09/32] PCI/PME: " Jiang Liu
2012-07-24 16:31 ` [RFC PATCH v2 10/32] PCI/AER: " Jiang Liu
2012-07-24 16:31 ` [RFC PATCH v2 11/32] PCI/ASPM: " Jiang Liu
2012-07-24 16:31 ` [RFC PATCH v2 12/32] PCI/ARM: " Jiang Liu
2012-07-24 16:31 ` [RFC PATCH v2 13/32] PCI/MIPS: " Jiang Liu
2012-07-24 16:31 ` [RFC PATCH v2 14/32] PCI/tile: " Jiang Liu
2012-07-24 16:31 ` [RFC PATCH v2 15/32] PCI/r8169: " Jiang Liu
2012-07-24 16:31 ` [RFC PATCH v2 16/32] PCI/broadcom: " Jiang Liu
2012-07-24 16:31 ` [RFC PATCH v2 17/32] PCI/igb: " Jiang Liu
2012-07-24 16:31 ` [RFC PATCH v2 18/32] PCI/vxge: " Jiang Liu
2012-07-24 16:31 ` [RFC PATCH v2 19/32] PCI/mlx4: " Jiang Liu
2012-07-24 16:31 ` [RFC PATCH v2 20/32] PCI/niu: " Jiang Liu
2012-07-24 16:31 ` [RFC PATCH v2 21/32] PCI/myri10ge: " Jiang Liu
2012-07-24 16:31 ` [RFC PATCH v2 22/32] PCI/chelsio: " Jiang Liu
2012-07-24 16:31 ` [RFC PATCH v2 23/32] PCI/atl1c: " Jiang Liu
2012-07-24 21:09 ` [RFC PATCH v2 00/32] provide interfaces to access PCIe capabilities registers Don Dutile
2012-07-29 2:26 ` Jiang Liu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=500FC011.5050807@huawei.com \
--to=jiang.liu@huawei.com \
--cc=bhelgaas@google.com \
--cc=ddutile@redhat.com \
--cc=izumi.taku@jp.fujitsu.com \
--cc=kaneshige.kenji@jp.fujitsu.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=liuj97@gmail.com \
--cc=rjw@sisk.pl \
--cc=wangyijing@huawei.com \
--cc=yinghai@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
Powered by JetHome