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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-77cfec3dadbsm1329619b3a.68.2025.09.17.23.40.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 17 Sep 2025 23:40:20 -0700 (PDT) Message-ID: <50346565-20d0-4ef9-80a5-e08070fdefb6@oss.qualcomm.com> Date: Thu, 18 Sep 2025 14:40:12 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 13/13] drm/msm/dp: Add support for lane mapping configuration To: Dmitry Baryshkov Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, fange.zhang@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, li.liu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, Bjorn Andersson , Konrad Dybcio References: <20250911-add-displayport-support-for-qcs615-platform-v4-0-2702bdda14ed@oss.qualcomm.com> <20250911-add-displayport-support-for-qcs615-platform-v4-13-2702bdda14ed@oss.qualcomm.com> From: Xiangxu Yin In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: 9DrpA3kZuX7N__E8E0_UmNsrEiPhkkU5 X-Proofpoint-ORIG-GUID: 9DrpA3kZuX7N__E8E0_UmNsrEiPhkkU5 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTE2MDIwMiBTYWx0ZWRfX3bRCyCg5vAsF SRC/pBpTC5AZRaPjECsaIblcVWdWescrhLLaThlvC2C+DHfuWNNyfpPjFuR5ZkDdXxHilcR+JBm OK+zlRFJL/8FZqclAjpHGEpRJtFUy5ITw4/JqunB4TVG0K7Kftqae/p2nKIZFIUU0Xnpu2OC/cM M5nmSYelwiiNoquwQUtVX/Cm55eIOyfliL1wg8Et/YtETyy9TEUS6wwIzTMWM87z41grWkjTCJ5 2mvwrpuInpIv5XQHQyG9Fsci2sFAoqhpnWmA3rDZsmeOE0zHQqYWmEiCb/KEakceX5kFX4OFgyP yuObtTVzCgFwgDtWG7TD184B6Zn/Rl4IEmSEi8B/U7+Trr/QSgi5Me5X2QlskJS2/XdxYv35z5g KgaOEdmD X-Authority-Analysis: v=2.4 cv=cf7SrmDM c=1 sm=1 tr=0 ts=68cba956 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=zEApyEmNphHiV2Xtq7IA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-17_01,2025-09-18_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 adultscore=0 bulkscore=0 priorityscore=1501 spamscore=0 phishscore=0 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509160202 On 9/12/2025 6:42 PM, Dmitry Baryshkov wrote: > On Thu, Sep 11, 2025 at 10:55:10PM +0800, Xiangxu Yin wrote: >> QCS615 platform requires non-default logical-to-physical lane mapping due >> to its unique hardware routing. Unlike the standard mapping sequence >> <0 1 2 3>, QCS615 uses <3 2 0 1>, which necessitates explicit >> configuration via the data-lanes property in the device tree. This ensures >> correct signal routing between the DP controller and PHY. >> >> Signed-off-by: Xiangxu Yin >> --- >> drivers/gpu/drm/msm/dp/dp_ctrl.c | 10 +++++----- >> drivers/gpu/drm/msm/dp/dp_link.c | 12 ++++++++++-- >> drivers/gpu/drm/msm/dp/dp_link.h | 1 + >> 3 files changed, 16 insertions(+), 7 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c >> index c42fd2c17a328f6deae211c9cd57cc7416a9365a..cbcc7c2f0ffc4696749b6c43818d20853ddec069 100644 >> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c >> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c >> @@ -423,13 +423,13 @@ static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctrl_private *ctrl) >> >> static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl_private *ctrl) >> { >> - u32 ln_0 = 0, ln_1 = 1, ln_2 = 2, ln_3 = 3; /* One-to-One mapping */ >> + u32 *lane_map = ctrl->link->lane_map; >> u32 ln_mapping; >> >> - ln_mapping = ln_0 << LANE0_MAPPING_SHIFT; >> - ln_mapping |= ln_1 << LANE1_MAPPING_SHIFT; >> - ln_mapping |= ln_2 << LANE2_MAPPING_SHIFT; >> - ln_mapping |= ln_3 << LANE3_MAPPING_SHIFT; >> + ln_mapping = lane_map[0] << LANE0_MAPPING_SHIFT; >> + ln_mapping |= lane_map[1] << LANE1_MAPPING_SHIFT; >> + ln_mapping |= lane_map[2] << LANE2_MAPPING_SHIFT; >> + ln_mapping |= lane_map[3] << LANE3_MAPPING_SHIFT; >> >> msm_dp_write_link(ctrl, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, >> ln_mapping); >> diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_link.c >> index caca947122c60abb2a01e295f3e254cf02e34502..7c7a4aa584eb42a0ca7c6ec45de585cde8639cb4 100644 >> --- a/drivers/gpu/drm/msm/dp/dp_link.c >> +++ b/drivers/gpu/drm/msm/dp/dp_link.c >> @@ -1242,6 +1242,7 @@ static int msm_dp_link_parse_dt(struct msm_dp_link *msm_dp_link) >> struct msm_dp_link_private *link; >> struct device_node *of_node; >> int cnt; >> + u32 lane_map[DP_MAX_NUM_DP_LANES] = {0}; >> >> link = container_of(msm_dp_link, struct msm_dp_link_private, msm_dp_link); >> of_node = link->dev->of_node; >> @@ -1255,10 +1256,17 @@ static int msm_dp_link_parse_dt(struct msm_dp_link *msm_dp_link) >> cnt = drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES); >> } >> >> - if (cnt > 0) >> + if (cnt > 0) { >> + struct device_node *endpoint; >> + >> msm_dp_link->max_dp_lanes = cnt; >> - else >> + endpoint = of_graph_get_endpoint_by_regs(of_node, 1, -1); >> + of_property_read_u32_array(endpoint, "data-lanes", lane_map, cnt); >> + } else { >> msm_dp_link->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes */ >> + } >> + >> + memcpy(msm_dp_link->lane_map, lane_map, msm_dp_link->max_dp_lanes * sizeof(u32)); > This will break all the cases when data-lanes is not present in DT: you > are storing the empty lane map instead of the 1:1 lane mapping that was > in place beforehand. You are right. It would overwrite the mapping with zeros when data-lanes is missing. In the next patch I will: 1. Initialize to a default 1:1 mapping (<0 1 2 3>). 2. Validate and apply data-lanes only if present and valid. 3. Always produce a full 4-lane mapping, filling unused lanes with remaining physical lanes. >> >> msm_dp_link->max_dp_link_rate = msm_dp_link_link_frequencies(of_node); >> if (!msm_dp_link->max_dp_link_rate)