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[86.58.6.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45e01575fadsm36130825e9.6.2025.09.11.11.45.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Sep 2025 11:45:27 -0700 (PDT) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Chen-Yu Tsai Cc: Andre Przywara , linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 5/7] clk: sunxi-ng: add support for the A523/T527 MCU CCU Date: Thu, 11 Sep 2025 20:45:26 +0200 Message-ID: <5037780.31r3eYUQgx@jernej-laptop> In-Reply-To: <20250911174710.3149589-6-wens@kernel.org> References: <20250911174710.3149589-1-wens@kernel.org> <20250911174710.3149589-6-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne =C4=8Detrtek, 11. september 2025 ob 19:47:08 Srednjeevropski poletni = =C4=8Das je Chen-Yu Tsai napisal(a): > From: Chen-Yu Tsai >=20 > The A523/T527 SoCs have a new MCU PRCM, which has more clocks and reset > controls for the RISC-V MCU and other peripherals. There is a second > audio PLL, but no bus clock dividers. The BSP driver uses the 24MHz main > oscillator as the parent for all the bus clocks. But the diagram > suggests busses from the other PRCM are used in this block as well. >=20 > Add a driver to support this part. Unlike the BSP driver, the SoC's main > MBUS clock is chosen as the parent for the MCU MBUS clock, and the > latter then serves as the parent of the MCU DMA controller's MBUS clock. > The bus gate clocks also use their respective bus clocks as parents > according to the system bus tree diagram. In cases where a block does > not appear in that diagram, an educated guess is made. >=20 > Signed-off-by: Chen-Yu Tsai > --- > Changes since v1: > - Added comment for "fixed" dividers in audio PLL clock > - Corrected variable names for audio PLL divider clocks > - Added comment for the reversed order of some of the DSP clock's > parents when compared to the manual > - Added comments for clocks and resets only found in the BSP driver > - Corrected register offset for i2s3-asrc and bus-mcu-pwm0 clocks > - Made "r-ahb" and new "r-apb0" external bus clocks the parents of the > bus gate clocks, with comments if guessed which one applies > - Moved .num_clks to after the list of clocks, making it obvious that > the value needs to be added if more clocks are added to the list Reviewed-by: Jernej Skrabec Best regards, Jernej