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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ad52d4ca2bfsm6455966b.157.2025.05.15.08.51.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 May 2025 08:51:34 -0700 (PDT) Message-ID: <503932a8-3124-4448-b18a-e25554745488@oss.qualcomm.com> Date: Thu, 15 May 2025 17:51:31 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFT v2 11/15] drm/msm/adreno: Switch to the common UBWC config struct To: Dmitry Baryshkov , Konrad Dybcio Cc: Bjorn Andersson , Rob Clark , Abhinav Kumar , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter , Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio References: <20250514-topic-ubwc_central-v2-0-09ecbc0a05ce@oss.qualcomm.com> <20250514-topic-ubwc_central-v2-11-09ecbc0a05ce@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: pCCtqx5NZYy1TnzmKmTWOObh2CFtnh8A X-Authority-Analysis: v=2.4 cv=Auju3P9P c=1 sm=1 tr=0 ts=68260d87 cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=hON3piRNd2u2ny3NyMoA:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 X-Proofpoint-GUID: pCCtqx5NZYy1TnzmKmTWOObh2CFtnh8A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE1MDE1NyBTYWx0ZWRfXxqiPNCPVfsgA qcFZO8eI0WcHlFKKczLkPrwrWodzeJFjv9qb45YQqj8pmLp3wPOimX89PeuNn5qe//J8djI0GpO 4gBVl36nLEFB5GXa89W8s5puitPh99zFt7S2EHFTVk0+HJTTJz/ju75tDuZuaO14VHwakYSKego nBPMcsvAO2HeZLkVPJgWLSaXYXqEv7D6mjGobnUQM/Wz9IA7W/mLz7Cua4zGezdfwS933VJ1qSu d8AS1uNZyMJj8du4KQn4LanRxAy/9iIdonJ/bAhun/sx6o2lsWmCJTtZeqy02FZBD2dmFFucI/f FewWG2Myk5WNaFySEpInGVfX1hvrhOP65U0fBPmOBR+EOMhHLCqiuHcAw7KPFpbfFGOHdr3WXm2 vIDNwzZICDxaNctEdlnyNemQSlOHW3r2NIK2KQNhpRJAqzAox+gtnjO7bZjFj8S8Td/16Aq+ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-15_06,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 spamscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 mlxscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 phishscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505150157 On 5/14/25 9:22 PM, Dmitry Baryshkov wrote: > On Wed, May 14, 2025 at 05:10:31PM +0200, Konrad Dybcio wrote: >> From: Konrad Dybcio >> >> Now that Adreno specifics are out of the way, use the common config >> (but leave the HBB hardcoding in place until that is wired up on the >> other side). >> >> Signed-off-by: Konrad Dybcio >> --- >> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 20 +++++------ >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 64 ++++++++++++++++----------------- >> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 ++-- >> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 45 ++++------------------- >> 4 files changed, 50 insertions(+), 85 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c >> index 650e5bac225f372e819130b891f1d020b464f17f..611e0eb26d0e19d431673d08e042162375fd400f 100644 >> --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c >> +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c >> @@ -833,8 +833,8 @@ static int a5xx_hw_init(struct msm_gpu *gpu) >> >> gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F); >> >> - BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); >> - hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13; >> + BUG_ON(adreno_gpu->ubwc_config->highest_bank_bit < 13); >> + hbb = adreno_gpu->ubwc_config->highest_bank_bit - 13; >> >> gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, hbb << 7); >> gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, hbb << 1); >> @@ -1754,6 +1754,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) >> struct msm_drm_private *priv = dev->dev_private; >> struct platform_device *pdev = priv->gpu_pdev; >> struct adreno_platform_config *config = pdev->dev.platform_data; >> + const struct qcom_ubwc_cfg_data *common_cfg; >> struct a5xx_gpu *a5xx_gpu = NULL; >> struct adreno_gpu *adreno_gpu; >> struct msm_gpu *gpu; >> @@ -1790,15 +1791,14 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) >> /* Set up the preemption specific bits and pieces for each ringbuffer */ >> a5xx_preempt_init(gpu); >> >> - /* Set the highest bank bit */ >> - if (adreno_is_a540(adreno_gpu) || adreno_is_a530(adreno_gpu)) >> - adreno_gpu->ubwc_config.highest_bank_bit = 15; >> - else >> - adreno_gpu->ubwc_config.highest_bank_bit = 14; >> + /* Inherit the common config and make some necessary fixups */ >> + common_cfg = qcom_ubwc_config_get_data(); >> + if (IS_ERR(common_cfg)) >> + return ERR_PTR(-EINVAL); >> >> - /* a5xx only supports UBWC 1.0, these are not configurable */ >> - adreno_gpu->ubwc_config.macrotile_mode = 0; >> - adreno_gpu->ubwc_config.ubwc_swizzle = 0x7; >> + /* Copy the data into the internal struct to drop the const qualifier (temporarily) */ >> + adreno_gpu->_ubwc_config = *common_cfg; >> + adreno_gpu->ubwc_config = &adreno_gpu->_ubwc_config; > > Ugh. I'd rather keep the ubwc config r/o. > >> >> adreno_gpu->uche_trap_base = 0x0001ffffffff0000ull; >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> index fdc843c47c075a92ec8305217c355e4ccee876dc..ae0bb7934e7ed203aa3b81e28767de204f0a4d60 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> @@ -587,64 +587,62 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) >> >> static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) >> { >> + const struct qcom_ubwc_cfg_data *common_cfg; >> + struct qcom_ubwc_cfg_data *cfg = &gpu->_ubwc_config; >> + >> /* Inherit the common config and make some necessary fixups */ >> - gpu->common_ubwc_cfg = qcom_ubwc_config_get_data(); >> - if (IS_ERR(gpu->common_ubwc_cfg)) >> + common_cfg = qcom_ubwc_config_get_data(); >> + if (IS_ERR(common_cfg)) >> return -EINVAL; >> >> - gpu->ubwc_config.ubwc_swizzle = 0x6; >> - gpu->ubwc_config.macrotile_mode = 0; >> - gpu->ubwc_config.highest_bank_bit = 15; >> + /* Copy the data into the internal struct to drop the const qualifier (temporarily) */ >> + *cfg = *common_cfg; >> + >> + cfg->ubwc_swizzle = 0x6; >> + cfg->highest_bank_bit = 15; >> > > This begs for WARN_ON(cfg->ubwc_swizzle != > gpu->common_ubwc_cfg->ubwc_swizzle) and similar change for HBB. Then > after testing we should be able to drop r/w part of the config. I'd rather put the warn in ubwc_config.c Konrad