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X-CSE-ConnectionGUID: L+zgozccSjmB7wYb2UkdvQ== X-CSE-MsgGUID: zfM4w3p5RVaikRLR+i542A== X-IronPort-AV: E=McAfee;i="6800,10657,11724"; a="74020634" X-IronPort-AV: E=Sophos;i="6.23,109,1770624000"; d="scan'208";a="74020634" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Mar 2026 12:27:05 -0700 X-CSE-ConnectionGUID: IEau2BNiSgaoC3eDR08bLA== X-CSE-MsgGUID: 3srBTWajS12dCgQr0wFt5A== X-ExtLoop1: 1 Received: from aduenasd-mobl5.amr.corp.intel.com (HELO [10.125.109.195]) ([10.125.109.195]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Mar 2026 12:27:03 -0700 Message-ID: <505a6bbd-3ecf-4de9-8fb9-0b21c3435a96@intel.com> Date: Mon, 9 Mar 2026 12:27:14 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] x86/cpu: Disable CR pinning during CPU bringup To: Tom Lendacky , Borislav Petkov Cc: Nikunj A Dadhania , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, tglx@kernel.org, mingo@redhat.com, dave.hansen@linux.intel.com, hpa@zytor.com, xin@zytor.com, seanjc@google.com, pbonzini@redhat.com, x86@kernel.org, sohil.mehta@intel.com, jon.grimm@amd.com References: <20260226092349.803491-1-nikunj@amd.com> <20260226092349.803491-2-nikunj@amd.com> <20260309134640.GOaa7PQJli_C9QATGB@fat_crate.local> <20260309161516.GAaa7yFMulhdzNQ-pt@fat_crate.local> <70644e1d-dd0e-4f0f-81c0-fd095e46e50b@intel.com> <7ca205d6-b01b-4ed3-959d-db31a6496d79@amd.com> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 3/9/26 11:40, Tom Lendacky wrote: > The SNP guest is dying in __x2apic_enable() when trying to read > MSR_IA32_APICBASE, which will trigger a #VC. > > If I set CR4[16] in cr4_init() then the SNP guest boots fine. That sounds pretty definitive. How does this work on the boot CPU? How does it manage to get FSGSBASE set up before __x2apic_enable()? Or is it on the early exception code, which might not use FSGSBASE instructions? Either way, I do think this needs to get fixed up. It was not acceptable for cr4_init() implicitly to set pinned features and then have the CPU boot code come along and do: cr4_set_bits(X86_CR4_FSGSBASE); It all basically worked by accident before.