From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9449F3446B0; Wed, 14 Oct 2026 06:41:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791960109; cv=none; b=GZ2Zel9yG4TmJ1qEpaDzuoeQIniUCUYNSCe/aWlWMzaCi+uWwZvcdbHQS8Cu7YOzSIPOkLrrhxnmItvPv+cSLlUWstG4BTIPnzKhzn1BrHSvE8pa1zCo26PAvIsGPYvSuNix0EY+xgyshG38PEvocB+GOaZg50iBFxauHWWolYM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791960109; c=relaxed/simple; bh=CrQ+7PL5630ATgxoE7VYa6LeS6ariIsX+2lERifN+3g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mAsHvXkl6msgFeesEu/gbrG8iqXu5hAjMz2m8l9UuUtZRk2hVoIa37V1rMzoVuLfnrlY/5Fb5ulmZkI0eUPgWOzjd7PPykZ/gdvTLw1FaWX0gC9GbtwdcvIId21EA8L5YqF3NeFZOQnb85mjRrL9FiAqdpFcptF9ybmUQ/C7Gr0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=ui1vHUCL; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="ui1vHUCL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1791960108; x=1823496108; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CrQ+7PL5630ATgxoE7VYa6LeS6ariIsX+2lERifN+3g=; b=ui1vHUCLWw+msAlCal1zuA6zOVskdIg2ILEFMmywV6HAlRt4oqucs0ll xlW4Ma4pmLoCUSd8cNfcNC7b6KC4OpoMaoKbD/LMFlW+R22SPeWd7TB1o iGZ9aFVDfE695Qfmj48IfzVlDvcJjwTalFT8zSwFdqTbiWy7xNxhWFMcz aVXyHaJw7Ms/hXbHp6aQUuKp4yDBYqtyiROwuHPD6jNHF34qc4dQ8aldR M2IA8ySqO2Fdasv15cly/1bP8orM7Euv+p9treoK7hqjdp6O3mBZqqD+C 0IAzlqsaxfBO/CjX63h3Gz6sPWV33bE6omM5okebbFzmPMlO8GRK5RtnU Q==; X-CSE-ConnectionGUID: +EHj4siaQ8GurLRgyclo+A== X-CSE-MsgGUID: GhMFTlAiRqWgt57Tpr1JAQ== X-IronPort-AV: E=Sophos;i="6.27,157,1787036400"; d="scan'208";a="232101723" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2026 23:41:47 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.49; Tue, 13 Oct 2026 23:41:46 -0700 Received: from che-ll-i67131.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 13 Oct 2026 23:41:38 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v8 7/8] ARM: dts: microchip: sama5d27_wlsom1: read MAC address from QSPI SFDP Date: Wed, 14 Oct 2026 12:10:11 +0530 Message-ID: <508a8707d550e4820d0281622ea4ac4e4fa07074.1790847519.git.manikandan.m@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Describe the QSPI flash SFDP as an NVMEM provider with the microchip,sst26vf-sfdp-eui layout, which exposes the factory-programmed EUI-48 as a "mac-address" cell, and point macb0 at it through nvmem-cells. This yields a stable MAC address on boards where U-Boot does not program one, instead of falling back to a random address. The sama5d27_wlsom1 SoM is fitted with the factory-programmed SST26VF064BEUI, and the QSPI flash node is only enabled on boards carrying that part, so the EUI-48 marker and its "mac-address" cell are always present. Boards without an EUI-programmed part simply do not reference the cell, so macb0 never defers waiting for it. Reviewed-by: Linus Walleij Signed-off-by: Manikandan Muralidharan --- arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi | 11 +++++++++++ .../boot/dts/microchip/at91-sama5d27_wlsom1_ek.dts | 2 ++ 2 files changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi index 6ce42a42a1bf..a4f55b2aa232 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi +++ b/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi @@ -238,6 +238,17 @@ qspi1_flash: flash@0 { m25p,fast-read; status = "disabled"; + sfdp { + compatible = "jedec,sfdp"; + + nvmem-layout { + compatible = "microchip,sst26vf-sfdp-eui"; + + mac_address_eui48: mac-address { + }; + }; + }; + partitions { compatible = "fixed-partitions"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1_ek.dts b/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1_ek.dts index 35a933eec573..5e87bf04bc47 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1_ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1_ek.dts @@ -97,6 +97,8 @@ uart6: serial@200 { &macb0 { status = "okay"; + nvmem-cells = <&mac_address_eui48>; + nvmem-cell-names = "mac-address"; }; &pioA { -- 2.43.0