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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-63c48ab560esm6477728a12.12.2025.10.20.04.51.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 20 Oct 2025 04:51:08 -0700 (PDT) Message-ID: <50ac4730-8c9c-49ae-8a1c-db4c8d87804e@oss.qualcomm.com> Date: Mon, 20 Oct 2025 13:51:07 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 06/24] arm64: dts: qcom: glymur: Enable pdp0 mailbox To: Sibi Sankar , Pankaj Patil , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250925-v3_glymur_introduction-v1-0-24b601bbecc0@oss.qualcomm.com> <20250925-v3_glymur_introduction-v1-6-24b601bbecc0@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: FsTuJM2iSgdLuEbWrkMoMaWmLG_Y6VP4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE4MDAyNyBTYWx0ZWRfXxBH+baAS44+x kkN4dgolBFDXpzGjMsWKKq1RPLxpz6t7jvHpaBZORzPl39yps6oxCL5L3UgvbViJvqV1H0LW5XL qTBRjwI3DF81ujQmDsbxj5NSyW1zdqAkt/Igo9Lz003qXLrFdmoOz/kft5H8O2fM0G1mEQ2U+MJ Q+Nah41lNaFr/+KQnSA5JMn4OYXADhIPuMenO+SF35qjA3b+6t+j0jOD0plvuCMxnpzo/0ETAIp HyLpJL/zPlP99OmBn87rXxjqqmUAXemdAANpmOp3ulJmExgOisDM+3k4Kb+f7LPxe58hHspyoTQ 7cdLw0ARgKE4X7vQUKlx0k1rf5wv5gRvFtWSF3pubSgMzzpE7P+u9jlnOYrZf/ko+/CxZqJk2jN plspgDnkFPFiBw6qYZ4UaNRGXRL+5g== X-Proofpoint-GUID: FsTuJM2iSgdLuEbWrkMoMaWmLG_Y6VP4 X-Authority-Analysis: v=2.4 cv=EYjFgfmC c=1 sm=1 tr=0 ts=68f6222f cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=WRDRb4xdkbWPci3HNeAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-20_02,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 spamscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 phishscore=0 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510180027 On 10/9/25 12:43 PM, Sibi Sankar wrote: > > On 9/25/2025 3:59 PM, Konrad Dybcio wrote: >> On 9/25/25 8:32 AM, Pankaj Patil wrote: >>> From: Sibi Sankar >>> >>> Enable pdp0 mailbox node on Glymur SoCs. >>> >>> Signed-off-by: Sibi Sankar >>> Signed-off-by: Pankaj Patil >>> --- >>>   arch/arm64/boot/dts/qcom/glymur.dtsi | 8 ++++++++ >>>   1 file changed, 8 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi >>> index 66a548400c720474cde8a8b82ee686be507a795f..ae013c64e096b7c90c0aa4cfc50f078a85518acb 100644 >>> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi >>> @@ -4065,6 +4065,14 @@ watchdog@17600000 { >>>               interrupts = ; >>>           }; >>>   +        pdp0_mbox: mailbox@17610000 { >>> +            compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; >>> +            reg = <0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>; >> 1 a line, please > > Hey Konrad, > > Thanks for taking time to review the series :) > > Will fix it in the next re-spin. > >>> +            interrupts = ; >> I see this has 3 channels, with 3 separate IRQs (but one pair of address >> spaces) - should we extend this description? > > It has a single IRQ and each bit corresponds to a channel.  The mbox theoretically > > hold as many channel as the number of bits. The third channel here is used for > > logging and is disabled on devices out in the wild. Your mailing client injects two '\n's every time you press enter Try setting mailnews.wraplength = 0 in your presumably thunderbird config Is the logging channel useful for us, on internal devices? We can still describe it if so > >> >>> +            #mbox-cells = <1>; >>> +            qcom,rx-chans = <0x7>; >> This further seems to confirm what I found (BIT(0) | BIT(1) | BIT(2) == 0x7) >> however this property doesn't exist upstream.. > > Ack, this seems to have picked up erroneously and isn't needed upstream and > > can be dropped safely. This was needed downstream because they share the > > same rx register space across multiple instances. This wouldn't be possible > > upstream and we would be exposing all mailboxes that uses the rx space in > > the same instance and extend mbox cells to 2 to support this in case when > > it is needed in the future. This won't fly, as you're essentially saying you're introducing knowingly incomplete bindings, which are supposed to stay immutable.. Konrad