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Thu, 23 Feb 2023 01:35:06 -0800 (PST) Received: from [192.168.1.109] ([178.197.216.144]) by smtp.gmail.com with ESMTPSA id u9-20020a5d5149000000b002c550eb062fsm8500225wrt.14.2023.02.23.01.35.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 23 Feb 2023 01:35:04 -0800 (PST) Message-ID: <50b6fb73-afb2-051b-7969-d7fbbe1e6175@linaro.org> Date: Thu, 23 Feb 2023 10:35:01 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v1 2/3] clk: starfive: Add StarFive JH7110 PLL clock driver Content-Language: en-US To: Xingyu Wu , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Philipp Zabel , Emil Renner Berthing Cc: Rob Herring , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Hal Feng , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org References: <20230221141147.303642-1-xingyu.wu@starfivetech.com> <20230221141147.303642-3-xingyu.wu@starfivetech.com> <3f50066b-f967-b9fa-1e0d-5337ec1ed194@linaro.org> <5e4007b7-6522-4c81-ca15-15a98c586aad@starfivetech.com> From: Krzysztof Kozlowski In-Reply-To: <5e4007b7-6522-4c81-ca15-15a98c586aad@starfivetech.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23/02/2023 10:32, Xingyu Wu wrote: > On 2023/2/23 16:56, Krzysztof Kozlowski wrote: >> On 21/02/2023 15:11, Xingyu Wu wrote: >>> Add driver for the StarFive JH7110 PLL clock controller and >>> modify the JH7110 system clock driver to rely on this PLL clocks. >>> >>> Signed-off-by: Xingyu Wu >>> --- >> >> >>> + >>> +static int jh7110_pll_clk_probe(struct platform_device *pdev) >>> +{ >>> + int ret; >>> + struct of_phandle_args args; >>> + struct regmap *pll_syscon_regmap; >>> + unsigned int idx; >>> + struct jh7110_clk_pll_priv *priv; >>> + struct jh7110_clk_pll_data *data; >>> + char *pll_name[JH7110_PLLCLK_END] = { >>> + "pll0_out", >>> + "pll1_out", >>> + "pll2_out" >>> + }; >>> + >>> + priv = devm_kzalloc(&pdev->dev, >>> + struct_size(priv, data, JH7110_PLLCLK_END), >>> + GFP_KERNEL); >>> + if (!priv) >>> + return -ENOMEM; >>> + >>> + priv->dev = &pdev->dev; >>> + ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, "starfive,sysreg", 0, 0, &args); >> >> 1. Wrong wrapping. Wrap code at 80 as coding style asks. >> >> 2. Why you are using syscon for normal, device MMIO operation? Your DTS >> also points that this is incorrect, hacky representation of hardware. >> Don't add devices to DT to fake places and then overuse syscon to fix >> that fake placement. The clock is in system registers, thus it must be >> there. >> >> 3. Even if this stays, why so complicated code instead of >> syscon_regmap_lookup_by_phandle()? >> > > Thanks for your advice. Will use syscon_regmap_lookup_by_phandle instead it > and remove useless part. So you ignored entirely part 2? This was the main comment... I am going to keep NAK-ing it then. Best regards, Krzysztof