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X-CSE-ConnectionGUID: K4PbgLyvRR6I5iLsjkvGKg== X-CSE-MsgGUID: 518xojIrTxiGmtb4gXUzyg== X-IronPort-AV: E=McAfee;i="6800,10657,11799"; a="91837815" X-IronPort-AV: E=Sophos;i="6.24,171,1774335600"; d="scan'208";a="91837815" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 May 2026 08:46:59 -0700 X-CSE-ConnectionGUID: cvTRD3XkQAWQb9GSODB5NA== X-CSE-MsgGUID: Z3/uBhh7St2PMGqtcabiIg== X-ExtLoop1: 1 Received: from soc-cp83kr3.clients.intel.com (HELO [10.122.185.5]) ([10.122.185.5]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 May 2026 08:46:57 -0700 Message-ID: <50bf1eb8-da2a-4df8-bd06-9dffb77b7e2b@intel.com> Date: Wed, 27 May 2026 10:46:56 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 1/2] perf pmu intel: Generalize SNC cpumask adjustment for multiple platforms To: Chun-Tse Shao , linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, james.clark@linaro.org, linux-perf-users@vger.kernel.org References: <20260515172710.428474-1-ctshao@google.com> Content-Language: en-US From: "Chen, Zide" In-Reply-To: <20260515172710.428474-1-ctshao@google.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 5/15/2026 12:26 PM, Chun-Tse Shao wrote: > Prepare for supporting more Intel platforms with sub-NUMA clustering by > generalizing the GNR specific logic. > > Signed-off-by: Chun-Tse Shao > --- Reviewed-by: Zide Chen > v6: > Make string literal. > Add SPR into SNC2. > > v5: lore.kernel.org/20260407203918.3178481-1-ctshao@google.com/ > Split patch. > > v4: lore.kernel.org/20260402205300.1953706-1-ctshao@google.com > Rebase. > > v3: lore.kernel.org/20260212223942.3832857-1-ctshao@google.com > Fix a typo. > > v2: lore.kernel.org/20260205232220.1980168-1-ctshao@google.com > Split EMR and GNR in the SNC2 IMC cpu map. > > v1: lore.kernel.org/20260108184430.1210223-1-ctshao@google.com > > tools/perf/arch/x86/util/pmu.c | 46 +++++++++++++++++++++------------- > 1 file changed, 29 insertions(+), 17 deletions(-) > > diff --git a/tools/perf/arch/x86/util/pmu.c b/tools/perf/arch/x86/util/pmu.c > index 7c9d238922a6..b8fab260c423 100644 > --- a/tools/perf/arch/x86/util/pmu.c > +++ b/tools/perf/arch/x86/util/pmu.c > @@ -22,20 +22,30 @@ > #include "util/env.h" > #include "util/header.h" > > -static bool x86__is_intel_graniterapids(void) > +#define GENUINE_INTEL_GNR "GenuineIntel-6-A[DE]" > + > +static bool x86__is_snc_supported(void) > { > - static bool checked_if_graniterapids; > - static bool is_graniterapids; > + static bool checked_if_snc_supported; > + static bool is_supported; > + > + if (!checked_if_snc_supported) { > > - if (!checked_if_graniterapids) { > - const char *graniterapids_cpuid = "GenuineIntel-6-A[DE]"; > + /* Graniterapids supports SNC configuration. */ > + static const char *const supported_cpuids[] = { > + GENUINE_INTEL_GNR, /* Graniterapids */ > + }; > char *cpuid = get_cpuid_str((struct perf_cpu){0}); > > - is_graniterapids = cpuid && strcmp_cpuid_str(graniterapids_cpuid, cpuid) == 0; > + for (size_t i = 0; i < ARRAY_SIZE(supported_cpuids); i++) { > + is_supported = cpuid && strcmp_cpuid_str(supported_cpuids[i], cpuid) == 0; > + if (is_supported) > + break; > + } > free(cpuid); > - checked_if_graniterapids = true; > + checked_if_snc_supported = true; > } > - return is_graniterapids; > + return is_supported; > } > > static struct perf_cpu_map *read_sysfs_cpu_map(const char *sysfs_path) > @@ -132,8 +142,8 @@ static int uncore_imc_snc(struct perf_pmu *pmu) > // Compute the IMC SNC using lookup tables. > unsigned int imc_num; > int snc_nodes = snc_nodes_per_l3_cache(); > - const u8 snc2_map[] = {1, 1, 0, 0, 1, 1, 0, 0}; > - const u8 snc3_map[] = {1, 1, 0, 0, 2, 2, 1, 1, 0, 0, 2, 2}; > + const u8 snc2_map[] = {1, 1, 0, 0}; > + const u8 snc3_map[] = {1, 1, 0, 0, 2, 2}; > const u8 *snc_map; > size_t snc_map_len; > > @@ -156,11 +166,12 @@ static int uncore_imc_snc(struct perf_pmu *pmu) > pr_warning("Unexpected: unable to compute IMC number '%s'\n", pmu->name); > return 0; > } > - if (imc_num >= snc_map_len) { > + if (imc_num >= snc_map_len * perf_cpu_map__nr(pmu->cpus)) { > pr_warning("Unexpected IMC %d for SNC%d mapping\n", imc_num, snc_nodes); > return 0; > } > - return snc_map[imc_num]; > + > + return snc_map[imc_num % snc_map_len]; > } > > static int uncore_cha_imc_compute_cpu_adjust(int pmu_snc) > @@ -200,7 +211,7 @@ static int uncore_cha_imc_compute_cpu_adjust(int pmu_snc) > return cpu_adjust[pmu_snc]; > } > > -static void gnr_uncore_cha_imc_adjust_cpumask_for_snc(struct perf_pmu *pmu, bool cha) > +static void uncore_cha_imc_adjust_cpumask_for_snc(struct perf_pmu *pmu, bool cha) > { > // With sub-NUMA clustering (SNC) there is a NUMA node per SNC in the > // topology. For example, a two socket graniterapids machine may be set > @@ -300,11 +311,12 @@ void perf_pmu__arch_init(struct perf_pmu *pmu) > pmu->mem_events = perf_mem_events_intel_aux; > else > pmu->mem_events = perf_mem_events_intel; > - } else if (x86__is_intel_graniterapids()) { > + } else if (x86__is_snc_supported()) { > if (strstarts(pmu->name, "uncore_cha_")) > - gnr_uncore_cha_imc_adjust_cpumask_for_snc(pmu, /*cha=*/true); > - else if (strstarts(pmu->name, "uncore_imc_")) > - gnr_uncore_cha_imc_adjust_cpumask_for_snc(pmu, /*cha=*/false); > + uncore_cha_imc_adjust_cpumask_for_snc(pmu, /*cha=*/true); > + else if (strstarts(pmu->name, "uncore_imc_") && > + !strstarts(pmu->name, "uncore_imc_free_running")) > + uncore_cha_imc_adjust_cpumask_for_snc(pmu, /*cha=*/false); > } > } > } > -- > 2.54.0.669.g59709faab0-goog > >