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Tue, 21 Oct 2025 23:37:32 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF7joNkznR+XIabkzzijhQowA5ro5PMScYqcqH+x0jynIzXiNCgZ6De5048CiOYXQThklmRMQ== X-Received: by 2002:a17:90b:52d0:b0:33b:bed8:891e with SMTP id 98e67ed59e1d1-33bcf8fa427mr25385841a91.19.1761115052001; Tue, 21 Oct 2025 23:37:32 -0700 (PDT) Received: from [10.217.217.147] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7a22ff34adasm13339717b3a.19.2025.10.21.23.37.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Oct 2025 23:37:31 -0700 (PDT) Message-ID: <50cee7dc-330b-4a4d-a49e-27f872e6556d@oss.qualcomm.com> Date: Wed, 22 Oct 2025 12:07:27 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] clk: qcom: camcc-sm6350: Fix PLL config of PLL2 To: Luca Weiss , Bjorn Andersson , Michael Turquette , Stephen Boyd , Konrad Dybcio , Danila Tikhonov Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20251021-agera-pll-fixups-v1-0-8c1d8aff4afc@fairphone.com> <20251021-agera-pll-fixups-v1-1-8c1d8aff4afc@fairphone.com> Content-Language: en-US From: Taniya Das In-Reply-To: <20251021-agera-pll-fixups-v1-1-8c1d8aff4afc@fairphone.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: O9VBNAufhZd4tA8b3GE_NV1N8Bx88hyt X-Proofpoint-GUID: O9VBNAufhZd4tA8b3GE_NV1N8Bx88hyt X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE5MDA5MCBTYWx0ZWRfX06m3hC40CrSD OkiefqrAkg9NJpD+5KB/4wela5kpF8VxJfS1594WMAeZCihy1PcLwPTlw0aMrZSoj6sSOVJWhin 2n4z6R77bpmuojuYVHMyGMIzM9tuC5P1OhfJg5rm7/787CTXTGLLH9/lky/k2SoMFAQSTuPlTG0 2WEcxiwk7qd7PpkGCl+BsvpndPja8g5dwZ0pnxrm9xL3M0lemZTgZUyONQhs3lAOQyw2BAyDtD9 r318FdMAK0I4LBCxewd1czLpfTYq3MAND+nzi0uiIOdzvfHMFJyzCAY0fdGQ5IrAQPzMuD5tSGz 0m/pNi0BoutnwZDcnjtuIya54ozaFgfD8llrFckHtWNDWWQRQz3oBs3pXm1XtQ3gTAJby4OfQdC tbyChuEJnuof80bP+1sHCi6xoGXHcQ== X-Authority-Analysis: v=2.4 cv=V5NwEOni c=1 sm=1 tr=0 ts=68f87bad cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=6H0WHjuAAAAA:8 a=rHO35cIvbrFS-cT-sPwA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 a=Soq9LBFxuPC4vsCAQt-j:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-22_02,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 suspectscore=0 clxscore=1015 phishscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510190090 On 10/21/2025 11:38 PM, Luca Weiss wrote: > The 'Agera' PLLs (with clk_agera_pll_configure) do not take some of the > parameters that are provided in the vendor driver. Instead the upstream > configuration should provide the final user_ctl value that is written to > the USER_CTL register. > > Fix the config so that the PLL is configured correctly, and fixes > CAMCC_MCLK* being stuck off. > > Fixes: 80f5451d9a7c ("clk: qcom: Add camera clock controller driver for SM6350") > Suggested-by: Taniya Das > Signed-off-by: Luca Weiss > --- > drivers/clk/qcom/camcc-sm6350.c | 6 +----- > 1 file changed, 1 insertion(+), 5 deletions(-) > > diff --git a/drivers/clk/qcom/camcc-sm6350.c b/drivers/clk/qcom/camcc-sm6350.c > index 8aac97d29ce3..87806392a59d 100644 > --- a/drivers/clk/qcom/camcc-sm6350.c > +++ b/drivers/clk/qcom/camcc-sm6350.c > @@ -145,15 +145,11 @@ static struct clk_alpha_pll_postdiv camcc_pll1_out_even = { > static const struct alpha_pll_config camcc_pll2_config = { > .l = 0x64, > .alpha = 0x0, > - .post_div_val = 0x3 << 8, > - .post_div_mask = 0x3 << 8, > - .aux_output_mask = BIT(1), > - .main_output_mask = BIT(0), > - .early_output_mask = BIT(3), > .config_ctl_val = 0x20000800, > .config_ctl_hi_val = 0x400003d2, > .test_ctl_val = 0x04000400, > .test_ctl_hi_val = 0x00004000, > + .user_ctl_val = 0x0000030b, > }; > > static struct clk_alpha_pll camcc_pll2 = { > Reviewed-by: Taniya Das -- Thanks, Taniya Das