From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755508AbcIAPQX (ORCPT ); Thu, 1 Sep 2016 11:16:23 -0400 Received: from mail-wm0-f49.google.com ([74.125.82.49]:37653 "EHLO mail-wm0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752807AbcIAPQU (ORCPT ); Thu, 1 Sep 2016 11:16:20 -0400 Subject: Re: [PATCH v2 1/5] mmu: extend the is_present check to 32 bits To: "Li, Liang Z" , Bandan Das , "kvm@vger.kernel.org" References: <1468361932-16580-1-git-send-email-bsd@redhat.com> <1468361932-16580-2-git-send-email-bsd@redhat.com> Cc: "guangrong.xiao@linux.intel.com" , "kernellwp@gmail.com" , "linux-kernel@vger.kernel.org" From: Paolo Bonzini Message-ID: <50ec82ef-eab1-13e5-3956-302f07419fb0@redhat.com> Date: Thu, 1 Sep 2016 17:16:09 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 01/09/2016 16:20, Li, Liang Z wrote: > Intel SDM doesn't describe whether the A bit will be set or not when > CPU accesses a no present EPT page table entry Bits in a non-present page table entry are entirely for use by the OS. The processor will never touch it. This includes both P=0 in non-EPT page tables and XWR=000 in EPT page tables. Paolo