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On 11/10/2025 4:55 PM, Krishna Chaitanya Chundru wrote: > From PCIe r6, sec 5.5.4 & Table 5-11 in sec 5.5.5 T_POWER_ON is the > minimum amount of time(in us) that each component must wait in L1.2.Exit > after sampling CLKREQ# asserted before actively driving the interface to > ensure no device is ever actively driving into an unpowered component and > these values are based on the components and AC coupling capacitors used > in the connection linking the two components. > > This property should be used to indicate the T_POWER_ON for each Root Port. > > Signed-off-by: Krishna Chaitanya Chundru > --- > Changes in V1: > - Updated the commit text (Mani). > > dtschema/schemas/pci/pci-bus-common.yaml | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pci/pci-bus-common.yaml > index 5257339..bbe5510 100644 > --- a/dtschema/schemas/pci/pci-bus-common.yaml > +++ b/dtschema/schemas/pci/pci-bus-common.yaml > @@ -152,6 +152,15 @@ properties: > This property is invalid in host bridge nodes. > maxItems: 1 > > + t-power-on-us: > + description: > + The minimum amount of time that each component must wait in > + L1.2.Exit after sampling CLKREQ# asserted before actively driving > + the interface to ensure no device is ever actively driving into an > + unpowered component. This value is based on the components and AC > + coupling capacitors used in the connection linking the two > + components(PCIe r6.0, sec 5.5.4). > + > supports-clkreq: > description: > If present this property specifies that CLKREQ signal routing exists from