From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA4323E2769; Wed, 30 Sep 2026 10:12:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790763142; cv=none; b=DOCYy3zUm1qTe2dk30PFUsluiKV7/B3onaYabfFpZRL+M3DmGbXuCf72IJDPRIXzGJ3C44TsV3CnsKgh1IThNTwPD/yiNg1u0XQWFWSJkk3nH3gKGwSLOqbztBHe+humcdOWg59dz+fKGEV6h/WYmQ0c/zzRW20gRivnwVGtlzo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790763142; c=relaxed/simple; bh=e2EiqEtrZ1QVkcER2vy49AcVi3JCtBleuVlk1SuHSqo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=u9HjF0L9veRGlGqPOpl0c1UPm9gnRLQQWXVZrR7tWUjmuHtI/WxWpAZ15YgL4ybYjvDYwz5RDl0zi0X0ZvSoJEI4NctJDJCTXjgpFINNIQd9SylI+CQGttqEdtXaA39jznlPF8NxZipZYFtVoMvpiJ/fp1NNVJilXVbwWah7xpw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=R7PSEE70; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="R7PSEE70" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Type:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To; bh=e2EiqEtrZ1QVkcER2vy49AcVi3JCtBleuVlk1SuHSqo=; b=R7PSEE70K/QFTnGHB9WIW4gzJc 1ylFt7T+MWYG5qEfkLdhthKgNWTrT0nMsJQ79ejoq6nXfOfR4GVRmY+EeEVUoZvG1iPZ1D17prYHL 0RXzRYXPYHt3EtkXtzTzpWKTrW+EMq0gKFLJaDDtzPL/h3RRwNowfSnX7h3l4DVifWlXY6I4uf1A7 1JEG90bi/jOCwWqixhWUnR743rng4WyQwfovKgU9x20lDMqrtqCLBCepb23bfEcSa52gqMHn2pLqe mDE2tnd1KVAsFMIOZjOBNjEKl8qxry72aGveQPMyTUdx7bOEmXmUkCryFovVt2jDg8GcmHtQT8jTb liz/qjGQ==; From: Heiko =?UTF-8?B?U3TDvGJuZXI=?= To: Vinod Koul , Manivannan Sadhasivam , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet , Michal Wilczynski Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , Uwe =?UTF-8?B?S2xlaW5lLUvDtm5pZw==?= , Michal Wilczynski Subject: Re: [PATCH v5 17/21] phy: Add common Innosilicon HDMI PHY helpers Date: Wed, 30 Sep 2026 12:11:50 +0200 Message-ID: <5147655.PYKUYFuaPT@diego> In-Reply-To: <20260929-jh7110-clean-send-v5-17-82b4d8e3c6c7@samsung.com> References: <20260929-jh7110-clean-send-v5-0-82b4d8e3c6c7@samsung.com> <20260929-jh7110-clean-send-v5-17-82b4d8e3c6c7@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Am Dienstag, 29. September 2026, 12:31:14 Mitteleurop=C3=A4ische Sommerzeit= schrieb Michal Wilczynski: > The Innosilicon HDMI PHY IP is used by several SoCs. They differ in > where the PHY register block sits in the register space and in which > pixel clocks they support, but the pre-PLL programming sequence and the > layout of its registers are the same. >=20 > Add a small library holding that shared part: the pre-PLL configuration > table format, a lookup, clk_ops determine_rate and recalc_rate helpers, > and the pre-PLL register programming. Callers pass a regmap, a register > offset for the PHY block, and their own pixel clock table. >=20 > No driver uses it yet; the users are converted separately. >=20 > Reviewed-by: Chaoyi Chen > Reviewed-by: Joshua Peisach > Signed-off-by: Michal Wilczynski Reviewed-by: Heiko Stuebner